900844 Datasheet, PDF (37/118 Pages) Freescale Semiconductor, Inc – Integrated Power Management IC for Ultra-mobile and Embedded Applications

FUNCTIONAL DEVICE OPERATION
SYSTEM CONTROL INTERFACE
Table 10. VIDEN Selections
VIDEN[1:0] Bits
Selection
0
0
0
1
1
0
1
1
Invalid
VCC
VNN
Unused
Both VCC and VNN have initial boot voltage (VCC V_BOOT = 1.1 V; VNN V_BOOT = 0.9 V) settings that the platform controller
hub sets to the VNN and VCC regulators by a SPI write to the VNNLATCH and VCCLATCH registers. Once all of the platform
voltage rails are up, the CPU will drive the VID and VIDEN signals to set the VNN and VCC output voltage to the appropriate
level. The VID and VIDEN signals will go through the sequence INVALID >> VNN >> INVALID >> VCC.
VID[6:0] and VIDEN[1:0] will transition together and the PMIC must de-bounce the VID[6:0] and VIDEN[1:0] for 100 to 400 ns.
The CPU will hold these signals valid for at least 500 ns. VID signals are disabled from controlling VCC/VNN unless the V_CCP
regulator is enabled
Both regulators support dynamic VID transitioning during normal runtime operation. Dynamic VIDs require the CPU to change
the VIDEN signals for the VNN regulator to INVALID each time, to change the VNN output voltage. The VCC regulator is different
in that it does not require the VIDEN signals to change to change the VCC output voltage. If the VIDEN signals are set for VCC
(01), the VID signals can change and the VCC regulator will respond by changing the output voltage accordingly.
Figure 13 shows how the VCC output voltage can change during normal runtime operation when the VIDEN signals are set
to VCC (01). If the VIDEN signals are set to VCC (01), the VCC regulator must monitor the VID signals, latch any changes, and
change the output voltage setting accordingly. When the CPU is dynamically changing the VID setting for the VCC regulator
during normal operation, it will only change the VID combination by 1 step, which corresponds to a voltage step of ±12.5 mV.
During these changes, the VCC regulator must follow the 25 mV/ms slew rate specification.
The VNN regulator differs from the VCC regulator, in that dynamic changes to the VNN regulator output voltage require the
VIDEN signals to change to INVALID each time. Figure 14 shows how the VNN output voltage can change during normal runtime
operation.
The VIDEN[1:0] pins are active high signals driven by the CPU to indicate if the VID bus is addressing VCC or VNN. They
follow the DC Signaling specifications in Table 3 with a reference of 1.05 V (V_CCPAOAC)
The VID[6:0] pins are active high signals driven by the CPU to indicate the output voltage setting for the VCC and VNN rails.
They follow the DC Signaling specifications in Table 3 with a reference of 1.05 V (V_CCP)
The VID output buffer driver is of the CMOS type. The platform controller hub output driver Impedance is a pull-up (55 Ω +20%/
-55%) and pull-down (55 Ω +20%/-55%). Motherboard Impedance is 55 Ω ±15%. Under extreme conditions, there could be
ringing that cross the 70/30% threshold, hence the de-bounce requirements. Maximum leakage current on the VID pins is
100 mA.
VID[6:0] for each of the VCC and VNN rails will be latched in an internal register that will be updated with every VID[6:0] pin
signaling.
Table 11. VCC and VNN Latch Register Structure and Bit Description
Name
Bits
Description
VCCVID
Reserved
FSLVCCLATCH (ADDR 0x1C9 - R - Default Value: 0x7F)
6:0
This register latches an Image of the last VID[6:0] signals for VCC
7
Reserved
VNNVID
Reserved
FSLVNNLATCH (ADDR 0x1CA - R - Default Value: 0x7F)
6:0
This register latches an Image of the last VID[6:0] signals for VNN
7
Reserved
Note that the term Reserved or RSVD is used throughout this document. This nomenclature refers to Reserved Registers that
are not for designed customer use. For question regarding these registers, contact Freescale Semiconductor Technical Support.
Analog Integrated Circuit Device Data
Freescale Semiconductor
900844
37