900844 Datasheet, PDF(91/118 Page) Freescale Semiconductor, Inc – Integrated Power Management IC for Ultra-mobile and Embedded Applications

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900844 Datasheet, PDF (91/118 Pages) Freescale Semiconductor, Inc – Integrated Power Management IC for Ultra-mobile and Embedded Applications

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FUNCTIONAL DEVICE OPERATION

ADC SUBSYSTEM

Table 58. Possible Reserved Channels Usage

Channel

ADC Input Signal

Application Supply (VPWR)

Reserved

Backup Voltage (VCOINCELL)

Reserved

Input Level

0 â 4.8 V

Reserved

0 â 3.6 V

Reserved

Scaling

Reserved

x2/3

Reserved

Scaled Version

0 â 2.4 V

Reserved

0 â 2.4 V

Reserved

Activating the prior channels to provide the signal specified occurs by asserting the following bits to 1. If the following bits are

0, then these channels are reserved:

â¢ VPWRCON for channel 22

â¢ LICON for channel 25

CONTROL

The ADC block consists of a 5-bit wide, 32-entry register file, which stores the address of the analog input for sampling. The

10-bit result is then stored in a separate register file 10+1 bits wide and 32 entries deep.

In order to operate the ADC, it has to be enabled first by setting the ADEN bit high in the ADCCNTL1 register. When the

register ADCCNTL1 ADSTRT bit is enabled, the PMIC will cycle through the 3 + 5 bit selector addresses in registers ADCADDRx.

The high 3-bits control the touch screen bias FETs, as described in Touch Screen Interface. The lower 5-bits address the ADC

selector to connect one of 32 channels to the ADC. The result of the ADC conversion is stored into the result registers

(ADCSNSx), along with the input gain setting (1 MSB). An address in the selector table of 0x1F designates the stop location of

the selection loop. At which point the interrupt flag bit 0 (RND), which can be masked through the MRND bit in the MADCINT

register, is set in register ADCINT, bit 1 of the INTERRUPT register (ADC) is set, and the external PMICINT signal is asserted,

if bit 1 of the INTMASK register is clear. The ADC sleeps for 0 to 27 ms as set by ADC register ADCCNTL1 through the

ADSLP[2:0] bits and then repeats the selector cycle. The new data overwrites the old in the result registers. At most, all 32 result

registers will be filled within 15.625 ms (2048/32 = 1/64 Hz). The result registers will not be read until the RND flag is set.

DEDICATED CHANNELS READING

Two different LSB value settings are possible by using the LSBSEL bit in the FSLADCCNTL register. LSBSEL = 0 is the

default setting. See Table 59 for more information

Table 59. ADC LSB Settings

# SELECT[4:0]

ADC INPUT SIGNAL

00000

00001

00010

00011

00100

00101

00110

PMIC Die Temperature

VCC Current Sense

VNN Current Sense

VCC180 Current Sense

Reserved

Battery Voltage (VBAT)

SIGNAL RANGE

1.2 â 2.4 V

4.2 A

1.9 A

0.5 A

Reserved

4.8 V

LSB VALUE

(LSBSEL = 0)

0.4244 K

4.1015 mA

1.8554 mA

0.4883 mA

Reserved

4.6875 mV

LSB VALUE

(LSBSEL = 1)

10 mA

Reserved

10 mV

Analog Integrated Circuit Device Data

Freescale Semiconductor

900844

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