900844 Datasheet, PDF (35/118 Pages) Freescale Semiconductor, Inc – Integrated Power Management IC for Ultra-mobile and Embedded Applications

FUNCTIONAL DEVICE OPERATION
SYSTEM CONTROL INTERFACE
RESET Pin
This is an active low, hard reset for the platform controller hub. When this pin is asserted, the platform controller hub returns
to its initial default state. This signal can be asserted when a cold or warm reset is initiated, depending on the settings in the
CHIPCNTL register.
The RESET pin follows the DC Signaling specifications in Table 3 with a VCC of 1.8 V (VPMIC)
PWRGD Pin
This is a Power Good output signal from the 900844 to the Platform controller hub. Assertion of PWRGD means that the
VCCPAOAC, VAON, and VPMIC rails have been valid for at least 100 microseconds. The Platform Controller Hub will remain
off until this signal is asserted. This signal is only de-asserted if VCCPAOAC, VAON, or VPMIC is out of regulation, or a cold
reset is initiated by the firmware.
The PWRGD pin follows the DC signaling specifications in Table 3 with a reference of 1.8 V (VPMIC)
WARM and COLD RESET
The RESET and PWRGD signals have two functions which are initiated through the register file. Together they define a warm
reset or cold reset to the platform controller hub. The sequencing shown in Figure 10 and is controlled from the register
CHIPCNTRL through bits WARMRST and COLDRST. The pulse will be held low for 5.0 μs < t < 31 μs.
Figure 10. Warm/Cold Reset Functionality
Table 9. CHIPCNTL Register Structure and Bit
Description
Name
Bits
Description
CHIPCNTL (ADDR 0x 06 - R/W - Default Value: 0x00)
COLDRST
0
Cold Reset Function Enable
x0 = No Change
x1 = Pulse RESET and PWRGD Low
WARMRST
1
Warm Reset Function Enable
x0 = No Change
x1 = Pulse RESET Low
Reserved
7:2 Reserved
EXITSTBY Pin
When the EXITSTBY pin is asserted high, the 900844 exits the AOAC standby settings for regulating the platform supplies.
When asserted, the PMIC switches the voltage regulators, as defined in the voltage regulator registers from the CTL bits to the
AOACTL bits. This is a low latency voltage regulators context switch.
EXITSTBY pin follows the DC signaling specifications in Table 3 with a reference of 1.05 V (V_CCP)
AOAC Exit Standby
When the EXITSTBY signal is asserted high from the Platform controller hub, the VRCOMP signal will be driven low. The
AOACTL bits will be copied to the CTL bits in the different voltage regulator control registers on the rising edge of the EXITSTBY
signal, unless Bit 5 is '0'. If Bit 5 is '0', then the CTL bits are not modified. The VRCOMP signal is de-asserted at this point. The
rails defined in the new CTL registers will be ramped up together or remain in the same state, as if the AOACTL settings were
the same as the previous CTL setting. Once all of the rails are in regulation, the VRCOMP signal will be driven high.
Figure 11 shows the timing diagram of the EXITSTBY signal. There is a special case (optimized case) when the EXITSTBY
signal is asserted with the VCCP, VCCPDDR, VCCA, and VCC180 rails. If some combination of these four rails turn on with the
assertion of the EXITSTBY signal, the entire time for the re-configuration should take no longer than 30 ms. See Figure 12.
Analog Integrated Circuit Device Data
Freescale Semiconductor
900844
35