900844 Datasheet, PDF (61/118 Pages) Freescale Semiconductor, Inc – Integrated Power Management IC for Ultra-mobile and Embedded Applications

FUNCTIONAL DEVICE OPERATION
POWER SUPPLIES
4
Figure 26. VNN Efficiency Curve
VNN Status/Control Registers and Bits Description
Reference the register map for read/write conditions and default state for each of these registers
Table 26. VNN Status and Control Registers Structure and Bits Description
Name
Bits
Description
CTLVNN
2:0
AOACCTLVNN 5:3
Reserved
7:6
VIDVNN
6:0
DVP1VRD
7
VNNCNT (ADDR 0x36 - R/W - Default value: 0x04)
VNN State Control
x0 = Reserved
x1 = Reserved
x2 = Reserved
x3 = Reserved
x4 = OFF
x5 = PFM
x6 = Automatic Pulse Skipping
x7 = PWM
VNN State Control during AOAC Exit (when the Exit pin is EXITSTBY pin is asserted). These bits will be initialized
by the system SPI controller after power up.
X0 = Do not copy
x1 = Do not copy
x2 = Do not copy
x3 = Do not copy
x4 = OFF
x5 = PFM
x6 = Automatic Pulse Skipping
x7 = PWM
Reserved
VNNLATCH (ADDR 0x33 - R/W - Default value: 0x7F)
VID VNN Control Through SPI. Signal codes are identical to the VID signal codes. Reference Figure 15 for more
details
VNN Register override enable bit.
X0 = VNN VID control follows the external pins
x1 = VNN VID control follows the VIDVNN control register bits
VDDQ
This is a 4.0 MHz fully integrated 2-switch synchronous Buck PWM voltage mode control DC/DC regulator.
The switcher can operate in different modes depending on the load conditions. These modes can be set through the SPI and
include a PFM mode, an Automatic Pulse Skipping mode, and a PWM mode.
VDDQ will be discharged every time the regulator is shutting down.
Analog Integrated Circuit Device Data
Freescale Semiconductor
900844
61