900844 Datasheet, PDF (88/118 Pages) Freescale Semiconductor, Inc – Integrated Power Management IC for Ultra-mobile and Embedded Applications

FUNCTIONAL DEVICE OPERATION
ADC SUBSYSTEM
Table 55. Input Power Interrupt/Mask Registers Structure and Bits Description
Name
Bits
Description
MBATDET
5
Battery Detection Interrupt Signal Mask
x0 = Unmask
x1 = Mask
RSVD
7:6 Reserved
SCHRGINT (ADDR 0XD2 - R - DEFAULT VALUE: 0X00)
Reserved
SBATOVP
STEMP
0
Reserved
1
Input voltage over-voltage Status
x0 = Input voltage is lower than the limit (< V_CHGCV + V_OVRVOLT)
x1 = Input voltage is higher than the limit (> V_CHGCV + V_OVRVOLT)
2
Battery temperature Status
x0 = Battery temperature is within valid window
x1 = Battery temperature is out of valid window
RSVD
RSVD
SBATDET
3
Reserved
4
Reserved
5
Battery Present Status Signal
x0 = Battery not present (VBAT < VTRKL)
x1 = Battery present (VBAT > VTRKL)
RSVD
7:6 Reserved
INPUT POWER PATH REGISTERS AND BITS DESCRIPTION
Table 56. FSL Charger Control Register Structure and Bits Description
Name
Bits
Description
FSLCHRGCNTL (ADDR 0X1D1 - R/W - DEFAULT VALUE: 0X13)
RSVD
COINCHEN
0 Reserved
1 ^{Coin cell Charger Enable/Disable}
x0 = Disable
x1 = Enable (Default)
VCOIN
4:2 ^{Coin cell Charger Output Voltage Setting}
x0 = 2.5 V
x1 = 2.7 V
x2 = 2.8 V
x3 = 2.9 V
x4 = 3.0 V (Default)
x5 = 3.1 V
x6 = 3.2 V
x7 = 3.3 V
Reserved
7:5 ^Reserved
ADC SUBSYSTEM
CONVERTER CORE
The ADC core is a 10 bit converter. The ADC core and logic run at an internally generated frequency of approximately
1.33 MHz. If an ADC conversion is requested while the PLL was not active, it will automatically be enabled by the ADC. A
32.768 kHz equivalent time base is derived from the 2.0 MHz clock to time ADC events. The ADC is supplied from VCORE. The
ADC core has an integrated auto calibration circuit which reduces the offset and gain errors.
900844
88
Analog Integrated Circuit Device Data
Freescale Semiconductor