900844 Datasheet, PDF (63/118 Pages) Freescale Semiconductor, Inc – Integrated Power Management IC for Ultra-mobile and Embedded Applications

• Uses internal compensation
• Gate drive circuits are supplied directly from VPWR
FUNCTIONAL DEVICE OPERATION
POWER SUPPLIES
Efficiency Curves
Figure 29 efficiency curves are calculated under PWM mode, based on the recommended external component values and
typical output voltage of 1.8 V. 3.0 V ≤ VPWR ≤ 4.4 V.
4
Figure 29. VDDQ Efficiency Curves
VDDQ Status/Control Registers and Bits Description
Reference the register map for read/write conditions and default state for each of these registers.
Table 27. VDDQ Status and Control Register Structure and Bits Description
Name
Bits
Description
CTLVDDQ
2:0
AOACCTLVDDQ 5:3
VDDQCNT (ADDR 0x37 - R/W - Default Value: 0x04)
VDDQ State Control
x0 = Reserved
x1 = Reserved
x2 = Reserved
x3 = Reserved
x4 = OFF
x5 = PFM
x6 = Automatic Pulse Skipping
x7 = PWM
VDDQ State Control during AOAC Exit (when EXITSTBY pin is asserted). These bits will be initialized by the
system SPI controller after power up.
X0 = Do not copy
x1 = Do not copy
x2 = Do not copy
x3 = Do not copy
x4 = OFF
x5 = PFM
x6 = Automatic Pulse Skipping
x7 = PWM
Reserved
7:6 ^Reserved
V21
This is a 4.0 MHz fully integrated 2-switch synchronous Buck PWM voltage-mode control DC/DC regulator.
The switcher can operate in different modes depending on the load conditions. These modes can be set through the SPI and
include a PFM mode, an Automatic Pulse Skipping mode, and a PWM mode. The previous selection is optimized to maximum
battery life based on load conditions.
V21 will be discharged every time the regulator is shutting down.
Analog Integrated Circuit Device Data
Freescale Semiconductor
900844
63