900844 Datasheet, PDF (59/118 Pages) Freescale Semiconductor, Inc – Integrated Power Management IC for Ultra-mobile and Embedded Applications

FUNCTIONAL DEVICE OPERATION
POWER SUPPLIES
4
Figure 24. VCC Efficiency Curve
VCC Status/Control Registers and Bits Description
Reference the register map for read/write conditions and default state for each of these registers.
Table 25. VCC Status Registers Structure and Bits Description
Name
Bits
Description
VCCCNT (ADDR 0X35 - R/W - DEFAULT VALUE: 0X24)
CTLVCC 2:0
AOACCTLVCC 5:3
VCC State Control
x0 = Reserved
x1 = Reserved
x2 = Reserved
x3 = Reserved
x4 = OFF
x5 = PFM
x6 = Automatic Pulse Skipping
x7 = PWM
VCC State Control during AOAC Exit (when Exit pin is EXITSTBY pin is asserted). These bits will be initialized by the
system SPI controller after power up.
X0 = Do not copy
x1 = Do not copy
x2 = Do not copy
x3 = Do not copy
x4 = OFF
x5 = PFM
x6 = Automatic Pulse Skipping
x7 = PWM
Reserved 7:6 Reserved
VCCLATCH (ADDR 0X32 - R/W - DEFAULT VALUE: 0X7F)
VIDVCC
6:0 ^{VID VCC Control Through SPI. Signal codes are identical to the VID signal codes. Reference Figures 15 for more}
details
DVP1VRD
7 ^{VCC Register override enable bit.}
X0 = VCC VID control follows the external pins
x1 = VCC VID control follows the VIDVCC control register bits
VNN
This is a VID controlled single-phase 1.0 MHz 2-switch synchronous Buck PWM voltage mode control DC/DC regulator,
designed to power high performance CPUs. VNN uses external MOSFETs, P-ch high side and N-ch low side.
VNN includes support for VID active voltage positioning requirements. A 7-bit DAC reads the VID input signals and sets the
output voltage level. The output voltage has a range of 0.3 to 1.2 V. The programming step size is 12.5 mV. Values will be read
in real time and will be stored in internal registers not accessible to the system host. Reference VIDEN[1:0] & VID[6:0] Pins.
Analog Integrated Circuit Device Data
Freescale Semiconductor
900844
59