900844 Datasheet, PDF (54/118 Pages) Freescale Semiconductor, Inc – Integrated Power Management IC for Ultra-mobile and Embedded Applications

FUNCTIONAL DEVICE OPERATION
POWER STATES AND CONTROL
Battery or Brick Inserted
VPWR
VCCPAOAC
Figure 19. 900844 Initial Power Up Sequence
Initial Power Up Sequence
Figure 19 shows the 900844 initial power up sequence:
1. A valid system voltage is applied
2. V_PWR ramps up
3. The 900844 internal circuits are powered
4. The 900844 turns on a minimal set of voltage rails as
outlined in Figure 19
5. SPI communication is ready
6. PMICINT pin is asserted
7. The system controller unit (SCU) reads the 900844
interrupt flag register (over SPI) to see why the 900844
interrupted the platform controller hub.
8. The SCU decides whether to boot the rest of the system,
or just run SCU code to manage various functions.
9. If the SCU decides to power up system, then CPU
(central processing unit) drives VNN VID,
VIDEN[1:0] = 10 to the 900844 and BSEL to the Platform
controller hub.
10. The 900844 drives CPU selected voltage for VNN
11. There will be no explicit signaling from the 900844 that
indicates that the VNN ramp has been complete.
12. VIDEN[1:0] is driven to 00 to avoid it switching from 10 to
01 directly.
13. The CPU drives the VCC boot VID on the VID pins. The
VIDEN[1:0] = 1 enables, only after HPLL has locked.
14. X86 Instruction Executions starts.
Table 22. 900844 Initial Power Up Timing
Parameter
Description
Min
Typ
Max
t₁
PMIC internal regulator Ramp-up
-
-
100 μs
t₂
V15 turn on delay
18 ms
-
550 ms
t₃
V15 Ramp-up
-
-
10 μs
t₄
VAON/VCCPAOAC turn on delay
0 μs
-
31 μs
t₅
VAON/VCCPAOAC ramp-up
-
-
700 μs
900844
54
Analog Integrated Circuit Device Data
Freescale Semiconductor