900844 Datasheet, PDF (7/118 Pages) Freescale Semiconductor, Inc – Integrated Power Management IC for Ultra-mobile and Embedded Applications

INTERNAL BLOCK DIAGRAM
Table 1. 900844 Pin Description
Node Name
Type
I/O Rating
# of
Balls
BGA Location
Pin Description
ADIN18
SGNL
I 4.8 V
1
ADIN19
SGNL
I 4.8 V
1
ADIN20
SGNL
I 4.8 V
1
ADIN21
SGNL
I 4.8 V
1
TSREF
LOPWR
- 3.6 V
1
GNDADC
LOPWRGND -
-
1
AJ17
AH16
W15
AC15
W17
V16
ADC generic input 9
ADC generic input 10
ADC generic input 11
ADC generic input 12
Reference for touchscreen interface
Ground reference for ADC
Oscillator and Real Time Clock - RTC
XTAL1
XTAL2
CLK32K
GNDRTC
SGNL
SGNL
SGNL
GND
I 2.5 V
1
O 2.5 V
1
O 3.6 V
1
-
-
1
AG19
AF18
AH22
AJ21
32.768 kHz oscillator crystal connection 1
32.768 kHz oscillator crystal connection 2
32 kHz clock output
Ground for the RTC block
Platform Architecture Sideband Signals
PMICINT
SGNL
O 2.5 V
1
B16
PMIC Interrupt. Asserted by PMIC to wake platform
controller hub and begin communications. Level-sensitive,
read to clear.
VRCOMP
SGNL
O 2.5 V
1
H16
Voltage regulator complete. Asserted high by the PMIC
when a SPI voltage regulation request has been decoded.
The signal is de-asserted on completion of the request (i.e.
the rail is in regulation).
RESETB
SGNL
O 2.5 V
1
C15
Active low hard reset for platform controller hub. When
asserted, the platform controller hub should return to its
initial default state.
PWRGD
SGNL
O 2.5 V
1
M16
POWER GOOD: The 900844 asserts this signal to indicate
that all power rails to the platform controller hub are good.
Assertion of PWRGD also means that VCCA_OSC has
been valid for at least 30 microseconds. The Platform
Controller Hub will remain “off” until this signal is asserted.
EXITSTBY
SGNL
I 2.5 V
1
J17
EXIT Standby. When asserted, the 900844 exits the AOAC
standby settings for regulating the platform supplies. When
asserted, the 900844 switches VRs on which are defined in
registers 0x09 through 0x0D. This is a low latency VR
context switch.
THERMTRIPB
SGNL
I 1.5 V
1
G17
Thermal trip. Asserted by the CPU to indicate a catastrophic
thermal event.
VIDEN0
VIDEN1
SGNL
SGNL
I 1.5 V
1
I 1.5 V
1
D4
Driven by the CPU to indicate which VR the VID bus is
addressed to (VCC or VNN). Debounced inside the 900844
E5
for 150 ns. The CPU will hold the value for at least 300 ns.
VID0
SGNL
I 1.5 V
1
E3
VID1
SGNL
I 1.5 V
1
H8
VID2
VID3
VID4
SGNL
SGNL
SGNL
I 1.5 V
1
I 1.5 V
1
I 1.5 V
1
E1
Driven by the CPU to indicate the output voltage setting for
J9
the VCC and VNN rails. Debounced inside the 900844 for
150 ns. The CPU will hold the value for at least 300 ns.
F4
VID5
SGNL
I 1.5 V
1
J7
VID6
GNDCTRL
SGNL
GND
I 1.5 V
1
-
-
1
F2
AB14
Logic Control Ground
Analog Integrated Circuit Device Data
Freescale Semiconductor
900844
7