900844 Datasheet, PDF (45/118 Pages) Freescale Semiconductor, Inc – Integrated Power Management IC for Ultra-mobile and Embedded Applications

FUNCTIONAL DEVICE OPERATION
CLOCK GENERATION AND REAL TIME CLOCK (RTC)
Table 18. Time, Calendar, and Alarm Data Modes
Address
location
Function
Decimal
Range
Range
Binary Data Mode
BCD Data Mode
Example ⁽¹⁷⁾
Binary Data BCD Data
Mode
Mode
0x10
Seconds
0-59
$00-$3B
$00-$59
15
21
0x11
Seconds Alarm
0-59
$00-$3B
$00-$59
15
21
0x12
Minutes
0-59
$00-$3B
$00-$59
3A
58
0x13
Minutes Alarm
0-59
$00-$3B
$00-$59
3A
58
0x14
Hours
0B
11
(12 Hour Mode)
1-12 $01-$0C(AM) / $81-$92(PM) $01-$12(AM) / $81-$92(PM)
(24 Hour Mode)
0-23
$00-$17
$00-$23
0x15
Hours Alarm
0B
11
(12 Hour Mode)
1-12 $01-$0C(AM) / $81-$92(PM) $01-$12(AM) / $81-$92(PM)
(24 Hour Mode)
0-23
$00-$17
$00-$23
0x16
Day of the Week
1-7
Sunday=1
$01-$07
$01-$07
05
05
0x17
Date of the Month
1-31
$01-$1F
$01-$31
0F
15
0x18
0x19
Month
Year
1-12
0-99
$01-$0C
$00-$63
$01-$12
$00-$99
02
02
08
08
Notes
17. Example: 11:58:21 Thursday 15 February 2008 (time is AM)
Reading the Time, Calendar, and Alarm
Under normal operation, the current time and date may be read by accessing the RTC registers through the system SPI. Since
the alarm is only updated by a SPI write instruction, the three alarm registers may be read at any time and will always be defined.
The 900844 SPI will run at a minimum of 12.5 MHz. Each individual SPI read transaction requires 25 cycles (less for burst-
read). The RTC contains seven timekeeping registers to keep track of seconds, minutes, hours, day-of-week, day-of-month,
month, and year. If the SPI is clocked at the slowest frequency, and the RTC is read using individual (not burst) SPI read
commands, the following equation gives the maximum amount of time it takes the processor to read a complete date and time
(assuming the reads are done sequentially, and uninterrupted): (25 * 7) / (12.5 MHz) = 14 μs.
This equation shows that a program which randomly accesses the time and date information will find the data in transition
statistically 14 times per million attempts. If a clock update occurs during the time it takes to read all seven timekeeping registers,
the values read may be inconsistent. In other words, if the program starts to read the seven date/time registers and an RTC
update occurs, the data collected may be in transition. In this event, it is possible to read transition data in one of the registers,
resulting in undefined output. It is more likely that the registers read after the update would be incremented (by one second), and
the registers read before the update would not.
The time, calendar, and alarm bytes are always accessible by the processor program. Once per second, the seven bytes are
advanced by one second and checked for an alarm condition. If any of the seven bytes are read at this time, the data outputs
should be considered undefined. Similarly, all seven bytes should be read between updates to get a consistent time and date.
Reading some of the bytes before an update and some after, may result in an erroneous output. The Update Cycle section
explains how to accommodate the update cycle in the processor program.
Update Cycle
The RTC module executes an update cycle once per second, assuming one of the proper time bases is in place, and the SET
bit in Register B is clear. The SET bit in the “1” state permits the program to initialize the time and calendar bytes, by stopping
an existing update and preventing a new one from occurring.
The primary function of the update cycle is to increment the Seconds byte, check for overflow, increment the Minutes byte
when appropriate, and so forth, up through the month and year bytes. The update cycle also compares each alarm byte with the
corresponding time byte, and issues an alarm if a match is present in all three positions.
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