MC9S08SH32CWL Datasheet, PDF (92/328 Pages) Freescale Semiconductor, Inc – MC9S08SH32 Series Features

Chapter 6 Parallel Input/Output Control
6.6.3.5 Port C Drive Strength Selection Register (PTCDS)
7
R
PTCDS7
W
6
PTCDS6
5
PTCDS5
4
PTCDS4
3
PTCDS3
2
PTCDS2
1
PTCDS1
Reset:
0
0
0
0
0
0
0
Figure 6-23. Drive Strength Selection for Port C Register (PTCDS)
Table 6-22. PTCDS Register Field Descriptions
0
PTCDS0
0
Field
Description
7:0
Output Drive Strength Selection for Port C Bits — Each of these control bits selects between low and high
PTCDS[7:0] output drive for the associated PTC pin. For port C pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port C bit n.
1 High output drive strength selected for port C bit n.
6.6.3.6 Ganged Output Drive Control Register (GNGC)
7
R
GNGPS7
W
Reset:
0
6
GNGPS6
5
GNGPS5
4
GNGPS4
3
GNGPS3
2
GNGPS2
1
GNGPS1
0
0
0
0
0
0
Figure 6-24. Ganged Output Drive Control Register (GNGC)
Table 6-23. GNGC Register Field Descriptions
0
GNGEN
0
Field
Description
7:1
GNGP[7:1]
Ganged Output Pin Select Bits— These write-once control bits selects whether the associated pin (see
Table 6-1for pins available) is enabled for ganged output. When GNGEN = 1, all enabled ganged output pins will
be controlled by the data, drive strength and slew rate settings for PTCO.
0 Associated pin is not part of the ganged output drive.
1 Associated pin is part of the ganged output drive. Requires GNGEN = 1.
0
GNGEN
Ganged Output Drive Enable Bit— This write-once control bit selects whether the ganged output drive feature
is enabled.
0 Ganged output drive disabled.
1 Ganged output drive enabled. PTC0 forced to output regardless of the value of PTCDD0 in PTCDD.
MC9S08SH32 Series Data Sheet, Rev. 2
92
Freescale Semiconductor
PRELIMINARY