MC9S08SH32CWL Datasheet, PDF (309/328 Pages) Freescale Semiconductor, Inc – MC9S08SH32 Series Features

Appendix A Electrical Characteristics
A.12.3 SPI
Table A-15 and Figure A-14 through Figure A-17 describe the timing requirements for the SPI system.
Table A-15. SPI Electrical Characteristic
Num¹ C
Rating²
Symbol
Min
Max
Unit
1
D Cycle time
Master t_SCK
2
Slave _tSCK
4
2048
t_cyc
—
t_cyc
2
D Enable lead time
Master _tLead
—
Slave _tLead
1/2
1/2
t_SCK
—
t_SCK
3
D Enable lag time
Master _tLag
—
Slave _tLag
1/2
1/2
t_SCK
—
t_SCK
4
D Clock (SPSCK) high time
Master and Slave
t_SCKH ^{1/2 t}SCK ^{– 25}
—
ns
5
D Clock (SPSCK) low time
Master and Slave
t_SCKL ^{1/2 t}SCK ^{– 25}
—
ns
6
D Data setup time (inputs)
Master _tSI(M)
30
Slave _tSI(S)
30
—
ns
—
ns
7
D Data hold time (inputs)
Master _tHI(M)
30
Slave _tHI(S)
30
8
D Access time, slave³
t_A
0
9
D Disable time, slave⁴
t_dis
—
—
ns
—
ns
40
ns
40
ns
10
D Data setup time (outputs)
Master _tSO
—
Slave _tSO
—
25
ns
25
ns
11
D Data hold time (outputs)
Master _tHO
–10
Slave _tHO
–10
—
ns
—
ns
12
D Operating frequency
Master
f_op
Slave
f_op
f_Bus/2048
dc
5⁵
f_Bus/4
MHz
1 _{Refer to Figure A-14 through Figure A-17.}
2 _{All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI}
pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output
pins.
3 _{Time to data active from high-impedance state.}
4 _{Hold time to high-impedance state.}
5 _{Maximum baud rate must be limited to 5 MHz due to input filter characteristics.}
MC9S08SH32 Series Data Sheet, Rev. 2
Freescale Semiconductor
309
PRELIMINARY