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MC9S08SH32CWL Datasheet, PDF (71/328 Pages) Freescale Semiconductor, Inc – MC9S08SH32 Series Features | |||
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Chapter 5 Resets, Interrupts, and General System Control
5.7.6 System Device Identiï¬cation Register (SDIDH, SDIDL)
These high page read-only registers are included so host development systems can identify the HCS08
derivative and revision number. This allows the development software to recognize where speciï¬c memory
blocks, registers, and control bits are located in a target MCU.
7
6
5
4
3
2
1
0
R
0
ID11
ID10
ID9
ID8
W
Reset:
01
â
â
â
0
0
0
0
= Unimplemented or Reserved
1 - Bit 7 is a mask option tie off that is used internally to determine that the device is a MC9S08SH32 Series.
Figure 5-7. System Device Identiï¬cation Register â High (SDIDH)
Table 5-8. SDIDH Register Field Descriptions
Field
Description
7
Bit 7 will read as a 0 for the MC9S08SH32 Series devices; writes have no effect.
6:4
Bits 6:4 are reserved. Reading these bits will result in an indeterminate value; writes have no effect.
Reserved
3:0
Part Identiï¬cation Number â Each derivative in the HCS08 Family has a unique identiï¬cation number. The
ID[11:8] MC9S08SH32 is hard coded to the value 0x01A. See also ID bits in Table 5-9.
R
W
Reset:
Field
7:0
ID[7:0]
7
6
5
4
3
2
1
0
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
0
0
0
1
1
0
1
0
= Unimplemented or Reserved
Figure 5-8. System Device Identiï¬cation Register â Low (SDIDL)
Table 5-9. SDIDL Register Field Descriptions
Description
Part Identiï¬cation Number â Each derivative in the HCS08 Family has a unique identiï¬cation number. The
MC9S08SH32 is hard coded to the value 0x01A. See also ID bits in Table 5-8.
MC9S08SH32 Series Data Sheet, Rev. 2
Freescale Semiconductor
71
PRELIMINARY
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