MC9S08SH32CWL Datasheet, PDF (29/328 Pages) Freescale Semiconductor, Inc – MC9S08SH32 Series Features

Chapter 2 Pins and Connections
Table 2-1. Pin Availability by Package Pin-Count
Pin Number
Lowest
Priority
Highest
28-pin 20-pin 16-pin Port Pin
Alt 1
Alt 2
Alt 3
Alt 4
Alt5
1
—
— PTC5
ADP13
2
—
— PTC4
3
1
1 PTA5
IRQ
TCLK
ADP12
RESET¹
4
2
2 PTA4
ACMPO
BKGD
MS
5
6
3
3
7
8
4
4
9
5
5 PTB7
10
6
6 PTB6
11
7
7 PTB5
12
8
8 PTB4
13
9
— PTC3
14
10
— PTC2
15
11
— PTC1
16
12
— PTC0
17
13
9 PTB3
18
14
10 PTB2
SCL²
SDA²
TPM1CH1³
TPM2CH1⁵
EXTAL
XTAL
SS
MISO
TPM1CH1³
TPM1CH0³
PIB3
PIB2
MOSI
SPSCK
V_DDA
V_SSA
V_DD
V_REFH
V_REFL
V_SS
PTC0⁴
PTC0⁴
PTC0⁴
PTC0⁴
PTC0⁴
PTC0⁴
PTC0⁴
PTC0⁴
ADP11
ADP10
ADP9
ADP8
ADP7
ADP6
19
15
11 PTB1
PIB1
TxD
ADP5
20
16
12 PTB0
21
—
— PTA7
22
—
— PTA6
23
17
13 PTA3
24
18
14 PTA2
25
19
15 PTA1
26
20
16 PTA0
PIB0
TPM2CH1⁵
TPM2CH0⁵
PIA3
PIA2
PIA1
PIA0
RxD
SCL²
SDA²
TPM2CH0⁵
TPM1CH0³
ADP4
ADP3
ADP2
ADP1⁶
ADP0⁶
ACMP-⁶
ACMP+⁶
27
—
— PTC7
ADP15
28
—
— PTC6
ADP14
1 _{Pin does not contain a clamp diode to VDD and should not be driven above VDD. The voltage measured on}
the internally pulled up RESET in will not be pulled to V_DD. The internal gates connected to this pin are
pulled to V_DD.
2 _{IIC pins can be repositioned using IICPS in SOPT2, default reset locations are PTA2, PTA3.}
3 _{TPM1CHx pins can be repositioned using T1CHxPS bits in SOPT2, default reset locations are PTA0, PTB5.}
4 _{This port pin is part of the ganged output feature. When pin is enabled for ganged output, it will have priority}
over all digital modules. The output data, drive strength and slew-rate control of this port pin will follow the
configuration for the PTC0 pin, even in 16-pin packages where PTC0 doesn’t bond out.
5 _{TPM2CHx pins can be repositioned using T2CHxPS bits in SOPT2, default reset locations are PTA1, PTB4.}
6 _{If ACMP and ADC are both enabled, both will have access to the pin.}
MC9S08SH32 Series Data Sheet, Rev. 2
Freescale Semiconductor
29
PRELIMINARY