MC9S08SH32CWL Datasheet, PDF (253/328 Pages) Freescale Semiconductor, Inc – MC9S08SH32 Series Features

Chapter 16 Timer/PWM Module (S08TPMV3)
Table 16-7. Mode, Edge, and Level Selection
CPWMS
0
1
MSnB:MSnA
00
01
1X
XX
ELSnB:ELSnA
01
10
11
01
10
11
10
X1
10
X1
Mode
Input capture
Output compare
Edge-aligned
PWM
Center-aligned
PWM
Configuration
Capture on rising edge
only
Capture on falling edge
only
Capture on rising or
falling edge
Toggle output on
compare
Clear output on
compare
Set output on compare
High-true pulses (clear
output on compare)
Low-true pulses (set
output on compare)
High-true pulses (clear
output on compare-up)
Low-true pulses (set
output on compare-up)
16.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL)
These read/write registers contain the captured TPM counter value of the input capture function or the
output compare value for the output compare or PWM functions. The channel registers are cleared by
reset.
7
6
5
4
3
2
R
Bit 15
14
13
12
11
10
W
1
0
9
Bit 8
Reset
0
0
0
0
0
0
0
0
Figure 16-13. TPM Channel Value Register High (TPMxCnVH)
7
6
5
4
3
2
1
0
R
Bit 7
6
5
4
3
2
1
Bit 0
W
Reset
0
0
0
0
0
0
0
0
Figure 16-14. TPM Channel Value Register Low (TPMxCnVL)
In input capture mode, reading either byte (TPMxCnVH or TPMxCnVL) latches the contents of both bytes
into a buffer where they remain latched until the other half is read. This latching mechanism also resets
MC9S08SH32 Series Data Sheet, Rev. 2
Freescale Semiconductor
253
PRELIMINARY