|
MC9S08SH32CWL Datasheet, PDF (188/328 Pages) Freescale Semiconductor, Inc – MC9S08SH32 Series Features | |||
|
◁ |
Chapter 12 Modulo Timer (S08MTIMV1)
12.3.1 MTIM Status and Control Register (MTIMSC)
MTIMSC contains the overï¬ow status ï¬ag and control bits which are used to conï¬gure the interrupt
enable, reset the counter, and stop the counter.
7
6
5
4
3
R
TOF
0
0
TOIE
TSTP
W
TRST
2
1
0
0
0
0
Reset:
0
0
0
1
0
0
0
0
Figure 12-4. MTIM Status and Control Register
Table 12-2. MTIM Status and Control Register Field Descriptions
Field
Description
7
TOF
6
TOIE
5
TRST
4
TSTP
3:0
MTIM Overï¬ow Flag â This read-only bit is set when the MTIM counter register overï¬ows to $00 after reaching
the value in the MTIM modulo register. Clear TOF by reading the MTIMSC register while TOF is set, then writing
a 0 to TOF. TOF is also cleared when TRST is written to a 1 or when any value is written to the MTIMMOD register.
0 MTIM counter has not reached the overï¬ow value in the MTIM modulo register.
1 MTIM counter has reached the overï¬ow value in the MTIM modulo register.
MTIM Overï¬ow Interrupt Enable â This read/write bit enables MTIM overï¬ow interrupts. If TOIE is set, then an
interrupt is generated when TOF = 1. Reset clears TOIE. Do not set TOIE if TOF = 1. Clear TOF ï¬rst, then set TOIE.
0 TOF interrupts are disabled. Use software polling.
1 TOF interrupts are enabled.
MTIM Counter Reset â When a 1 is written to this write-only bit, the MTIM counter register resets to $00 and TOF
is cleared. Reading this bit always returns 0.
0 No effect. MTIM counter remains at current state.
1 MTIM counter is reset to $00.
MTIM Counter Stop â When set, this read/write bit stops the MTIM counter at its current value. Counting resumes
from the current value when TSTP is cleared. Reset sets TSTP to prevent the MTIM from counting.
0 MTIM counter is active.
1 MTIM counter is stopped.
Unused register bits, always read 0.
MC9S08SH32 Series Data Sheet, Rev. 2
188
Freescale Semiconductor
PRELIMINARY
|
▷ |