MC9S08SH32CWL Datasheet, PDF (177/328 Pages) Freescale Semiconductor, Inc – MC9S08SH32 Series Features

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Chapter 11 Internal Clock Source (S08ICSV2)
Table 11-5. ICS Status and Control Register Field Descriptions (continued)
Description
OSC Initialization — If the external reference clock is selected by ERCLKEN or by the ICS being in FEE, FBE,
or FBELP mode, and if EREFS is set, then this bit is set after the initialization cycles of the external oscillator
clock have completed. This bit is only cleared when either ERCLKEN or EREFS are cleared.
ICS Fine Trim — The FTRIM bit controls the smallest adjustment of the internal reference clock frequency.
Setting FTRIM will increase the period and clearing FTRIM will decrease the period by the smallest amount
possible.
11.4 Functional Description
11.4.1 Operational Modes
FLL Bypassed
External Low
Power(FBELP)
IREFS=0
CLKS=10
BDM Disabled
and LP=1
IREFS=0
CLKS=10
BDM Enabled
or LP =0
FLL Bypassed
External (FBE)
IREFS=1
CLKS=00
FLL Engaged
Internal (FEI)
FLL Engaged
External (FEE)
IREFS=0
CLKS=00
IREFS=1
CLKS=01
BDM Enabled
or LP=0
FLL Bypassed
Internal (FBI)
FLL Bypassed
Internal Low
Power(FBILP)
IREFS=1
CLKS=01
BDM Disabled
and LP=1
Entered from any state
when MCU enters stop
Stop
Returns to state that was active
before MCU entered stop, unless
RESET occurs while in stop.
Figure 11-7. Clock Switching Modes
The seven states of the ICS are shown as a state diagram and are described below. The arrows indicate the
allowed movements between the states.
11.4.1.1 FLL Engaged Internal (FEI)
FLL engaged internal (FEI) is the default mode of operation and is entered when all the following
conditions occur:
MC9S08SH32 Series Data Sheet, Rev. 2
Freescale Semiconductor
177
PRELIMINARY