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MC9S08SH32CWL Datasheet, PDF (152/328 Pages) Freescale Semiconductor, Inc – MC9S08SH32 Series Features | |||
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Chapter 10 Inter-Integrated Circuit (S08IICV2)
10.1.4 Block Diagram
Figure 10-2 is a block diagram of the IIC.
Address
ADDR_DECODE
Interrupt
Data Bus
DATA_MUX
CTRL_REG FREQ_REG ADDR_REG
STATUS_REG
DATA_REG
Input
Sync
Clock
Control
Start
Stop
Arbitration
Control
In/Out
Data
Shift
Register
Address
Compare
SCL
SDA
Figure 10-2. IIC Functional Block Diagram
10.2 External Signal Description
This section describes each user-accessible pin signal.
10.2.1 SCL â Serial Clock Line
The bidirectional SCL is the serial clock line of the IIC system.
10.2.2 SDA â Serial Data Line
The bidirectional SDA is the serial data line of the IIC system.
10.3 Register Deï¬nition
This section consists of the IIC register descriptions in address order.
MC9S08SH32 Series Data Sheet, Rev. 2
152
PRELIMINARY
Freescale Semiconductor
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