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MC9S08SH32CWL Datasheet, PDF (171/328 Pages) Freescale Semiconductor, Inc – MC9S08SH32 Series Features | |||
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Chapter 11 Internal Clock Source (S08ICSV2)
11.1.2 Features
Key features of the ICS module follow. For device speciï¬c information, refer to the ICS Characteristics in
the Electricals section of the documentation.
⢠Frequency-locked loop (FLL) is trimmable for accuracy
â 0.1% resolution using internal 32kHz reference and 9-bit TRIM:FTRIM
â 2% deviation over voltage and temperature using internal 32kHz reference
⢠Internal or external reference clocks up to 5MHz can be used to control the FLL
â 3 bit select for reference divider is provided
⢠Internal reference clock has 9 trim bits available
⢠Internal or external reference clocks can be selected as the clock source for the MCU
⢠Whichever clock is selected as the source can be divided down
â 2 bit select for clock divider is provided
â Allowable dividers are: 1, 2, 4, 8
â BDC clock is provided as a constant divide by 2 of the DCO output
⢠Control signals for a low power oscillator as the external reference clock are provided
â HGO, RANGE, EREFS, ERCLKEN, EREFSTEN
⢠FLL Engaged Internal mode is automatically selected out of reset
11.1.3 Block Diagram
Figure 11-2 is the ICS block diagram.
MC9S08SH32 Series Data Sheet, Rev. 2
Freescale Semiconductor
171
PRELIMINARY
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