MC9S08SH32CWL Datasheet, PDF (105/328 Pages) Freescale Semiconductor, Inc – MC9S08SH32 Series Features

Chapter 7 Central Processor Unit (S08CPUV3)
Table 7-2. Instruction Set Summary (Sheet 4 of 9)
Source
Form
Operation
CMP #opr8i
CMP opr8a
CMP opr16a
CMP oprx16,X
CMP oprx8,X
CMP ,X
CMP oprx16,SP
CMP oprx8,SP
IMM
DIR
Compare Accumulator with Memory
A–M
(CCR Updated But Operands Not Changed)
EXT
IX2
IX1
IX
SP2
SP1
COM opr8a
COMA
COMX
COM oprx8,X
COM ,X
COM oprx8,SP
Complement
M ← (M)= $FF – (M) DIR
(One’s Complement) A ← (A) = $FF – (A) INH
X ← (X) = $FF – (X) INH
M ← (M) = $FF – (M) IX1
M ← (M) = $FF – (M) IX
M ← (M) = $FF – (M) SP1
CPHX opr16a
CPHX #opr16i
CPHX opr8a
CPHX oprx8,SP
Compare Index Register (H:X) with Memory
(H:X) – (M:M + $0001)
(CCR Updated But Operands Not Changed)
EXT
IMM
DIR
SP1
CPX #opr8i
CPX opr8a
CPX opr16a
CPX oprx16,X
CPX oprx8,X
CPX ,X
CPX oprx16,SP
CPX oprx8,SP
IMM
DIR
Compare X (Index Register Low) with
EXT
Memory
IX2
X–M
IX1
(CCR Updated But Operands Not Changed) IX
SP2
SP1
DAA
Decimal Adjust Accumulator
After ADD or ADC of BCD Values
INH
DBNZ opr8a,rel
DBNZA rel
DBNZX rel
DBNZ oprx8,X,rel
DBNZ ,X,rel
DBNZ oprx8,SP,rel
DIR
Decrement A, X, or M and Branch if Not Zero
(if (result) ≠ 0)
DBNZX Affects X Not H
INH
INH
IX1
IX
SP1
DEC opr8a
Decrement M ← (M) – $01
DIR
DECA
A ← (A) – $01
INH
DECX
X ← (X) – $01
INH
DEC oprx8,X
M ← (M) – $01
IX1
DEC ,X
M ← (M) – $01
IX
DEC oprx8,SP
M ← (M) – $01
SP1
DIV
Divide
A ← (H:A)÷(X); H ← Remainder
INH
EOR #opr8i
Exclusive OR Memory with Accumulator
IMM
EOR opr8a
A ← (A ⊕ M)
DIR
EOR opr16a
EXT
EOR oprx16,X
IX2
EOR oprx8,X
IX1
EOR ,X
IX
EOR oprx16,SP
SP2
EOR oprx8,SP
SP1
Object Code
Cyc-by-Cyc
Details
Affect
on CCR
V11H INZC
A1 ii
B1 dd
C1 hh ll
D1 ee ff
E1 ff
F1
9E D1 ee ff
9E E1 ff
2 pp
3 rpp
4 prpp
4 prpp
3 rpp
3 rfp
5 pprpp
4 prpp
↕11– –↕↕↕
33 dd
43
53
63 ff
73
9E 63 ff
5 rfwpp
1p
1p
5 rfwpp
4 rfwp
6 prfwpp
011– –↕↕1
3E hh ll
65 jj kk
75 dd
9E F3 ff
6 prrfpp
3 ppp
5 rrfpp
6 prrfpp
↕11– –↕↕↕
A3 ii
B3 dd
C3 hh ll
D3 ee ff
E3 ff
F3
9E D3 ee ff
9E E3 ff
2 pp
3 rpp
4 prpp
4 prpp
3 rpp
3 rfp
5 pprpp
4 prpp
↕11– –↕↕↕
72
1p
U11– –↕↕↕
3B dd rr
4B rr
5B rr
6B ff rr
7B rr
9E 6B ff rr
3A dd
4A
5A
6A ff
7A
9E 6A ff
7 rfwpppp
4 fppp
4 fppp
7 rfwpppp
6 rfwppp
8 prfwpppp
5 rfwpp
1p
1p
5 rfwpp
4 rfwp
6 prfwpp
–11– ––––
↕11– –↕↕–
52
6 fffffp
–11– ––↕↕
A8 ii
B8 dd
C8 hh ll
D8 ee ff
E8 ff
F8
9E D8 ee ff
9E E8 ff
2 pp
3 rpp
4 prpp
4 prpp
3 rpp
3 rfp
5 pprpp
4 prpp
011– –↕↕–
MC9S08SH32 Series Data Sheet, Rev. 2
Freescale Semiconductor
105
PRELIMINARY