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MC705P6ACPE Datasheet, PDF (91/98 Pages) Freescale Semiconductor, Inc – M68HC05 Microcontrollers
tVDDR
VDD
VDD THRESHOLD (1-2 V TYPICAL)
OSC1(2)
INTERNAL
PROCESSOR
CLOCK(1)
INTERNAL
ADDRESS
BUS(1)
INTERNAL
DATA
BUS(1)
4064 tcyc
tcyc
1FFE
1FFF NEW PC NEW PC
NEW
NEW
PCH
PCL
OP
CODE
RESET
1FFE
1FFE
1FFE
1FFE
1FFF NEW PC NEW PC
tRL
NOTE 3
PCH
PCL
OP
CODE
Notes:
1. Internal timing signal and bus information are not available externally.
2. OSC1 line is not meant to represent frequency. It is only used to represent time.
3. The next rising edge of the internal clock following the rising edge of RESET initiates the reset sequence.
Figure 14-2. Power-On Reset and External Reset Timing Diagram