MC705P6ACPE Datasheet, PDF (33/98 Pages) Freescale Semiconductor, Inc – M68HC05 Microcontrollers

Chapter 5
Interrupts
5.1 Introduction
The MCU can be interrupted six different ways:
1. Non-maskable software interrupt instruction (SWI)
2. External asynchronous interrupt (IRQ)
3. Input capture interrupt (TIMER)
4. Output compare interrupt (TIMER)
5. Timer overflow interrupt (TIMER)
6. Port A interrupt (if selected via mask option register)
Interrupts cause the processor to save the register contents on the stack and to set the interrupt mask (I
bit) to prevent additional interrupts. Unlike reset, hardware interrupts do not cause the current instruction
execution to be halted, but are considered pending until the current instruction is completed.
When the current instruction is completed, the processor checks all pending hardware interrupts. If
interrupts are not masked (I bit in the condition code register is clear) and the corresponding interrupt
enable bit is set, the processor proceeds with interrupt processing. Otherwise, the next instruction is
fetched and executed. The SWI is executed the same as any other instruction, regardless of the I-bit state.
When an interrupt is to be processed, the CPU puts the register contents on the stack, sets the I bit in the
CCR, and fetches the address of the corresponding interrupt service routine from the vector table at
locations $1FF8 through $1FFF. If more than one interrupt is pending when the interrupt vector is fetched,
the interrupt with the highest vector location shown in Table 5-1 will be serviced first.
Table 5-1. Vector Addresses for Interrupts and Reset
Register
N/A
N/A
N/A
TSR
TSR
TSR
Flag
Name
N/A
N/A
N/A
ICF
OCF
TOF
Interrupts
Reset
Software
External Interrupt
Timer Input Capture
Timer Output Compare
Timer Overflow
CPU
Interrupt
RESET
SWI
IRQ
TIMER
TIMER
TIMER
Vector
Address
$1FFE–$1FFF
$1FFC–$1FFD
$1FFA–$1FFB
$1FF8–$1FF9
$1FF8–$1FF9
$1FF8–$1FF9
An RTI instruction is used to signify when the interrupt software service routine is completed. The RTI
instruction causes the CPU state to be recovered from the stack and normal processing to resume at the
next instruction that was to be executed when the interrupt took place. Figure 5-1 shows the sequence of
events that occurs during interrupt processing.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
33