MC705P6ACPE Datasheet, PDF (40/98 Pages) Freescale Semiconductor, Inc – M68HC05 Microcontrollers

Input/Output Ports
Table 6-1. Port A I/O Functions
DDRA
I/O Pin Mode
Accesses to
DDRA @ $0004
Read/Write
0
IN, Hi-Z
DDRA0–DDRA7
1
OUT
DDRA0–DDRA7
Note: Does not affect input, but stored to data register
Accesses to Data
Register @ $0000
Read
Write
I/O Pin
See Note
PA0–PA7
PA0–PA7
Table 6-2. Port B I/O Functions
DDRB
I/O Pin Mode
Accesses to
DDRB @ $0005
Read/Write
0
IN, Hi-Z
DDRB5–DDRB7
1
OUT
DDRB5–DDRB7
Note: Does not affect input, but stored to data register
Accesses to Data
Register @ $0001
Read
Write
I/O Pin
See Note
PB5–PB7 PB5–PB7
Table 6-3. Port C I/O Functions
DDRC
I/O Pin Mode
Accesses to
DDRC @ $0006
Read/Write
0
IN, Hi-Z
DDRC0–DDRC7
1
OUT
DDRC0–DDRC7
Note: Does not affect input, but stored to data register
Accesses to Data
Register @ $0002
Read
Write
I/O Pin
See Note
PC0–PC7 PC0–PC7
Table 6-4. Port D I/O Functions
DDRD
I/O Pin Mode
Accesses to
DDRD @ $0007
Read/Write
0
IN, Hi-Z
DDRD5
1
OUT
DDRD5
Notes:
1. Does not affect input, but stored to data register
2. PD7 is input only
Accesses to Data
Register @ $0003
Read
Write
I/O Pin
See Note 1
PD5
PD5
NOTE
To avoid generating a glitch on an I/O port pin, data should be written to the
I/O port data register before writing a logic 1 to the corresponding data
direction register.
At power-on or reset, all DDRs are cleared, which configures all port pins as inputs. The DDRs are
capable of being written to or read by the processor. During the programmed output state, a read of the
data register will actually read the value of the output data latch and not the level on the I/O port pin.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
40
Freescale Semiconductor