MC705P6ACPE Datasheet, PDF (56/98 Pages) Freescale Semiconductor, Inc – M68HC05 Microcontrollers

Analog Subsystem
9.7 A/D Subsystem Operation during Halt/Wait Modes
The A/D subsystem continues normal operation during wait and halt modes. To decrease power
consumption during wait or halt mode, the ADON and ADRC bits in the A/D status and control register
should be cleared if the A/D subsystem is not being used.
9.8 A/D Subsystem Operation during Stop Mode
When stop mode is enabled, execution of the STOP instruction will terminate all A/D subsystem functions.
Any pending conversion is aborted. When the oscillator resumes operation upon leaving stop mode, a
finite amount of time passes before the A/D subsystem stabilizes sufficiently to provide conversions at its
rated accuracy. The delays built into the MC68HC705P6A when coming out of stop mode are sufficient
for this purpose. No explicit delays need to be added to the application software.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
56
Freescale Semiconductor