MC705P6ACPE Datasheet, PDF (50/98 Pages) Freescale Semiconductor, Inc – M68HC05 Microcontrollers

Capture/Compare Timer
8.3.5 Input Capture Registers
When a selected edge occurs on the TCAP pin, the current high and low bytes of the 16-bit counter are
latched into the input capture registers. Reading ICRH before reading ICRL inhibits further capture until
ICRL is read. Reading ICRL after reading the status register clears the input capture flag (ICF). Writing to
the input capture registers has no effect.
Address:
Read:
Write:
Address:
Write:
ICRH — $0014
Bit 7
6
ICRH7 ICRH6
5
ICRH5
4
ICRH4
3
ICRH3
2
ICRH2
1
ICRH1
Unaffected by reset
ICRL — $0015
Bit 7
6
5
4
3
2
1
Unaffected by reset
= Unimplemented
Figure 8-6. Input Capture Registers (ICRH and ICRL)
Bit 0
ICRH0
Bit 0
NOTE
To prevent interrupts from occurring between readings of ICRH and ICRL,
set the interrupt flag in the condition code register before reading ICRH, and
clear the flag after reading ICRL.
8.3.6 Output Compare Registers
When the value of the 16-bit counter matches the value in the output compare registers, the planned
TCMP pin action takes place. Writing to OCRH before writing to OCRL inhibits timer compares until OCRL
is written. Reading or writing to OCRL after the timer status register clears the output compare flag (OCF).
Address:
Write:
Read:
OCRH — $0016
Bit 7
6
OCRH7 OCRH6
5
OCRH5
4
3
OCRH4 OCRH3
Unaffected by reset
2
OCRH2
1
OCRH1
Bit 0
OCRH0
Address: OCRL — $0017
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Unaffected by reset
Figure 8-7. Output Compare Registers (OCRH and OCRL)
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
50
Freescale Semiconductor