MC705P6ACPE Datasheet, PDF (28/98 Pages) Freescale Semiconductor, Inc – M68HC05 Microcontrollers

Operating Modes
RESET
1
IRQ/V_PP
2
PA7
3
PA6
4
PA5
5
PA4
6
PA3
7
PA2
8
PA1
9
PA0
10
SDO/PB5
11
SDI/PB6
12
SCK/PB7
13
V_SS
14
28
V_DD
27
OSC1
26
OSC2
25
PD7/TCAP
24
TCMP
23
PD5
22
PC0
21
PC1
20
PC2
19
PC3/AD3
18
PC4/AD2
17
PC5/AD1
16
PC6/AD0
15
PC7/V_REFH
Figure 3-1. User Mode Pinout
3.4 Low-Power Modes
The MC68HC705P6A is capable of running in a low-power mode in each of its configurations. The WAIT
and STOP instructions provide three modes that reduce the power required for the MCU by stopping
various internal clocks and/or the on-chip oscillator. The SWAIT bit in the MOR is used to modify the
behavior of the STOP instruction from stop mode to halt mode. The flow of the stop, halt, and wait modes
is shown in Figure 3-2.
3.4.1 STOP Instruction
The STOP instruction can result in one of two modes of operation depending on the state of the SWAIT
bit in the MOR. If the SWAIT bit is clear, the STOP instruction will behave like a normal STOP instruction
in the M68HC05 Family and place the MCU in stop mode. If the SWAIT bit in the MOR is set, the STOP
instruction will behave like a WAIT instruction (with the exception of a brief delay at startup) and place the
MCU in halt mode.
3.4.1.1 Stop Mode
Execution of the STOP instruction when the SWAIT bit in the MOR is clear places the MCU in its lowest
power consumption mode. In stop mode, the internal oscillator is turned off, halting all internal processing,
including the COP watchdog timer. Execution of the STOP instruction automatically clears the I bit in the
condition code register so that the IRQ external interrupt is enabled. All other registers and memory
remain unaltered. All input/output lines remain unchanged.
The MCU can be brought out of stop mode only by an IRQ external interrupt or an externally generated
RESET. When exiting stop mode, the internal oscillator will resume after a 4064 internal clock cycle
oscillator stabilization delay.
NOTE
Execution of the STOP instruction when the SWAIT bit in the MOR is clear
will cause the oscillator to stop, and, therefore, disable the COP watchdog
timer. To avoid turning off the COP watchdog timer, stop mode should be
changed to halt mode by setting the SWAIT bit in the MOR. See 3.5 COP
Watchdog Timer Considerations for additional information.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
28
Freescale Semiconductor