MC705P6ACPE Datasheet, PDF (49/98 Pages) Freescale Semiconductor, Inc – M68HC05 Microcontrollers

Timer I/O Registers
8.3.3 Timer Registers
The timer registers (TRH and TRL), shown in Figure 8-4, contains the current high and low bytes of the
16-bit counter. Reading TRH before reading TRL causes TRL to be latched until TRL is read. Reading
TRL after reading the timer status register clears the timer overflow flag (TOF). Writing to the timer
registers has no effect.
Address:
Read:
Write
Reset:
TRH — $0018
Bit 7
6
TRH7
TRH6
1
1
5
TRH5
1
4
TRH4
1
3
TRH3
1
2
TRH2
1
1
TRH1
1
Bit 0
TRH0
1
Address: TRL — $0019
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
1
1
1
1
1
1
0
0
= Unimplemented
Figure 8-4. Timer Registers (TRH and TRL)
8.3.4 Alternate Timer Registers
The alternate timer registers (ATRH and ATRL), shown in Figure 8-5, contain the current high and low
bytes of the 16-bit counter. Reading ATRH before reading ATRL causes ATRL to be latched until ATRL
is read. Reading ATRL has no effect on the timer overflow flag (TOF). Writing to the alternate timer
registers has no effect.
Address:
Read:
Write:
Reset:
ATRH — $001A
Bit 7
6
ACRH7 ACRH6
1
1
5
ACRH5
1
4
ACRH4
1
3
ACRH3
1
2
ACRH2
1
1
ACRH1
1
Bit 0
ACRH0
1
Address: ATRL — $001B
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
1
1
1
1
1
1
0
0
= Unimplemented
Figure 8-5. Alternate Timer Registers (ATRH and ATRL)
NOTE
To prevent interrupts from occurring between readings of ATRH and ATRL,
set the interrupt flag in the condition code register before reading ATRH,
and clear the flag after reading ATRL.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
49