MC705P6ACPE Datasheet, PDF (39/98 Pages) Freescale Semiconductor, Inc – M68HC05 Microcontrollers

Port D
READ $0006
WRITE $0006
WRITE $0002
RESET
(RST)
DATA DIRECTION
REGISTER BIT
DATA
REGISTER BIT
I/O
OUTPUT
PIN
READ $0002
INTERNAL HC05
DATA BUS
Figure 6-3. Port C I/O Circuitry
6.5 Port D
Port D is a 2-bit port with one bidirectional pin (PD5) and one input-only pin (PD7). Pin PD7 is shared with
the 16-bit timer. The port D data register is located at address $0003 and its data direction register (DDR)
is located at address $0007. The contents of the port D data register are indeterminate at initial powerup
and must be initialized by user software. Reset does not affect the data registers, but clears the DDRs,
thereby setting PD5 to input mode. Writing a 1 to DDR bit 5 sets PD5 to output mode (see Figure 6-4).
Port D may be used for general I/O applications regardless of the state of the 16-bit timer. Since PD7 is
an input-only line, its state can be read from the port D data register at any time.
READ $0007
WRITE $0007
WRITE $0003
RESET
(RST)
READ $0003
DATA DIRECTION
REGISTER BIT
DATA
REGISTER BIT
I/O
OUTPUT
PIN
INTERNAL HC05
DATA BUS
Figure 6-4. Port D I/O Circuitry
6.6 I/O Port Programming
Each pin on port A through port D (except pin 7 of port D) can be programmed as an input or an output
under software control as shown in Table 6-1, Table 6-2, Table 6-3, and Table 6-4. The direction of a pin
is determined by the state of its corresponding bit in the associated port data direction register (DDR). A
pin is configured as an output if its corresponding DDR bit is set to a logic 1. A pin is configured as an
input if its corresponding DDR bit is cleared to a logic 0.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
39