MC705P6ACPE Datasheet, PDF (67/98 Pages) Freescale Semiconductor, Inc – M68HC05 Microcontrollers

Chapter 12
Central Processor Unit (CPU) Core
12.1 Introduction
The MC68HC705P6A has an 8-K memory map. Therefore, it uses only the lower 13 bits of the address
bus. In the following discussion, the upper three bits of the address bus can be ignored. Also, the STOP
instruction can be modified to place the MCU in either the normal stop mode or the halt mode by means
of a MOR bit. All other instructions and registers behave as described in this section.
12.2 Registers
The MCU contains five registers which are hard-wired within the CPU and are not part of the memory
map. These five registers are shown in Figure 12-1 and are described in the following paragraphs.
7 6 5 432 1 0
ACCUMULATOR
A
INDEX REGISTER
X
15 14 13 12 11 10 9 8
0000000011
STACK POINTER
SP
PROGRAM COUNTER
PC
CONDITION CODE REGISTER
111H I NZC
CC
HALF-CARRY BIT (FROM BIT 3)
INTERRUPT MASK
NEGATIVE BIT
ZERO BIT
CARRY BIT
Figure 12-1. MC68HC05 Programming Model
12.2.1 Accumulator
The accumulator is a general-purpose 8-bit register as shown in Figure 12-1. The CPU uses the
accumulator to hold operands and results of arithmetic calculations or non-arithmetic operations. The
accumulator is unaffected by a reset of the device.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
67