MC705P6ACPE Datasheet, PDF (54/98 Pages) Freescale Semiconductor, Inc – M68HC05 Microcontrollers

Analog Subsystem
9.4.1 Conversion Times
Each input conversion requires 32 internal clock cycles, which must be at a frequency equal to or greater
than 1 MHz.
9.4.2 Internal versus External Oscillator
If the internal clock is 1 MHz or greater (i.e., external oscillator 2 MHz or greater), the internal RC oscillator
must be turned off and the external oscillator used as the conversion clock.
If the MCU internal clock frequency is less than 1 MHz (2 MHz external oscillator), the internal RC
oscillator (approximately 1.5 MHz) must be used for the A/D converter clock. The internal RC clock is
selected by setting the ADRC bit in the ADSC register.
When the internal RC oscillator is being used, these limitations apply:
1. Since the internal RC oscillator is running asynchronously with respect to the internal clock, the
conversion complete bit (CC) in register ADSC must be used to determine when a conversion
sequence has been completed.
2. Electrical noise will slightly degrade the accuracy of the A/D converter. The A/D converter is
synchronized to read voltages during the quiet period of the clock driving it. Since the internal and
external clocks are not synchronized, the A/D converter will occasionally measure an input when
the external clock is making a transition.
9.4.3 Multi-Channel Operation
An input multiplexer allows the A/D converter to select from one of four external analog signals. Port C
pins PC3 through PC6 are shared with the inputs to the multiplexer.
9.5 A/D Status and Control Register (ADSC)
The ADSC register reports the completion of A/D conversion and provides control over oscillator
selection, analog subsystem power, and input channel selection. See Figure 9-1.
Address: $001E
Bit 7
6
5
4
Read: CC
0
ADRC ADON
Write:
Reset: 0
0
0
0
= Unimplemented
3
2
1
Bit 0
0
CH2
CH1
CH0
0
0
0
0
Figure 9-1. A/D Status and Control Register (ADSC)
CC — Conversion Complete
This read-only status bit is set when a conversion sequence has completed and data is ready to be
read from the ADC register. CC is cleared when the ADSC is written to or when data is read from the
ADC register. Once a conversion has been started, conversions of the selected channel will continue
every 32 internal clock cycles until the ADSC register is written to again. During continuous conversion
operation, the ADC register will be updated with new data, and the CC bit set every 32 internal clock
cycles. Also, data from the previous conversion will be overwritten regardless of the state of the CC bit.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
54
Freescale Semiconductor