MC705P6ACPE Datasheet, PDF (32/98 Pages) Freescale Semiconductor, Inc – M68HC05 Microcontrollers

Resets
The POR will generate the RST signal and reset the MCU. If any other reset function is active at the end
of this 4064 internal clock cycle delay, the RST signal will remain active until the other reset condition(s)
end.
4.3.2 Computer Operating Properly (COP) Reset
When the COP watchdog timer is enabled (COP bit in the MOR is set), the internal COP reset is
generated automatically by a timeout of the COP watchdog timer. This timer is implemented with an
18-stage ripple counter that provides a timeout period of 65.5 ms when a 4-MHz oscillator is used. The
COP watchdog counter is cleared by writing a logical 0 to bit zero at location $1FF0.
The COP watchdog timer can be disabled by clearing the COP bit in the MOR or by applying 2 x V_DD to
the IRQ/V_PP pin (for example, during bootloader). When the IRQ/V_PP pin is returned to its normal
operating voltage range (between V_SS–V_DD), the COP watchdog timer’s output will be restored if the COP
bit in the mask option register (MOR) is set.
The COP register is shared with the least significant byte (LSB) of an unused vector address as shown
in Figure 4-2. Reading this location will return the programmed value of the unused user interrupt vector,
usually 0. Writing to this location will clear the COP watchdog timer.
Address: $1FF0
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
0
0
0
0
Write:
COPR
= Unimplemented
Figure 4-2. Unused Vector and COP Watchdog Timer
When the COP watchdog timer expires, it will generate the RST signal and reset the MCU. If any other
reset function is active at the end of the COP reset signal, the RST signal will remain in the reset condition
until the other reset condition(s) end. When the reset condition ends, the MCU’s operating mode will be
selected (see Table 3-1. Operating Mode Conditions After Reset).
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
32
Freescale Semiconductor