MC705P6ACPE Datasheet, PDF (69/98 Pages) Freescale Semiconductor, Inc – M68HC05 Microcontrollers

Registers
I — Interrupt Mask Bit
When the interrupt mask is set, the internal and external interrupts are disabled. Interrupts are enabled
when the interrupt mask is cleared. When an interrupt occurs, the interrupt mask is automatically set
after the CPU registers are saved on the stack, but before the interrupt vector is fetched. If an interrupt
request occurs while the interrupt mask is set, the interrupt request is latched. Normally, the interrupt
is processed as soon as the interrupt mask is cleared.
A return from interrupt (RTI) instruction pulls the CPU registers from the stack, restoring the interrupt
mask to its state before the interrupt was encountered. After any reset, the interrupt mask is set and
can only be cleared by the clear I bit (CLI), STOP, or WAIT instructions.
N — Negative Bit
The negative bit is set when the result of the last arithmetic operation, logical operation, or data
manipulation was negative. (Bit 7 of the result was a logic one.)
The negative bit can also be used to check an often-tested flag by assigning the flag to bit 7 of a
register or memory location. Loading the accumulator with the contents of that register or location then
sets or clears the negative bit according to the state of the flag.
Z — Zero Bit
The zero bit is set when the result of the last arithmetic operation, logical operation, data manipulation,
or data load operation was zero.
C — Carry/Borrow Bit
The carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred during the last
arithmetic operation, logical operation, or data manipulation. The carry/borrow bit is also set or cleared
during bit test and branch instructions and during shifts and rotates. This bit is not set by an INC or
DEC instruction.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
69