MC705P6ACPE Datasheet, PDF (64/98 Pages) Freescale Semiconductor, Inc – M68HC05 Microcontrollers

Mask Option Register (MOR)
LEVEL — IRQ Edge Sensitivity
If the LEVEL bit is clear, the IRQ/V_PP pin will only be sensitive to the falling edge of the signal applied
to the IRQ/V_PP pin. If the LEVEL bit is set, the IRQ/V_PP pin will be sensitive to both the falling edge of
the input signal and the logic low level of the input signal on the IRQ/V_PP pin.
LSBF — SIOP Least Significant Bit First
If the LSBF bit is set, the serial data to and from the SIOP will be transferred least significant bit first.
If the LSBF bit is clear, the serial data to and from the SIOP will be transferred most significant bit first.
SPR0 and SPR1 — SIOP Clock Rate
The SPR0 and SPR1 bits determine the clock rate used to transfer the serial data to and from the
SIOP. The various clock rates available are given in Table 11-1.
Table 11-1. SIOP Clock Rate
SPR1
0
0
1
1
SPR0
0
1
0
1
SIOP Master Clock
f_osc ÷ 64
f_osc ÷ 32
f_osc ÷ 16
f_osc ÷ 8
SWAIT — STOP Instruction Mode
Setting the SWAIT bit will prevent the STOP instruction from stopping the on-board oscillator. Clearing
the SWAIT bit will permit the STOP instruction to stop the on-board oscillator and place the MCU in
stop mode. Executing the STOP instruction when SWAIT is set will place the MCU in halt mode. See
3.4.1 STOP Instruction for additional information.
SECURE — Security State⁽¹⁾
If SECURE bit is set, the EPROM is locked.
PA(0:7)PU — Port A Pullups/Interrupt Enable/Disable
If any PA(0:7)PU is selected, that pullup/interrupt is enabled. The interrupt sensitivity will be selected
via the LEVEL bit in the same way as the IRQ pin.
NOTE
The port A pullup/interrupt function is NOT available on the ROM device,
MC68HC05P6.
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the EPROM/OTPROM
difficult for unauthorized users.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
64
Freescale Semiconductor