MC705P6ACPE Datasheet, PDF (63/98 Pages) Freescale Semiconductor, Inc – M68HC05 Microcontrollers

Chapter 11
Mask Option Register (MOR)
11.1 Introduction
The mask option register (MOR) contains two bytes of EPROM used to enable or disable each of the
features controlled by mask options on the MC68HC05P6 (a ROM version of the MC68HC705P6A).
The seven programmable options on the MC68HC705P6A are:
1. COP watchdog timer (enable or disable)
2. IRQ triggering (edge- or edge- and level-sensitive)
3. SIOP data bit order (most significant bit or least significant bit first)
4. SIOP clock rate (OSC divided by 8, 16, 32, or 64)
5. Stop instruction mode (stop mode or halt mode)
6. Secure EPROM from external reading
7. Keyscan interrupt/pullups on PA0–PA7
11.2 Mask Option Register
Mask options are programmed into the mask option register (MOR) by the firmware in the bootloader
ROM. See Figure 11-1.
Address: $1EFF
Bit 7
Read:
PA7PU
Write:
Erased State:
0
6
PA6PU
0
5
PA5PU
0
4
PA4PU
0
3
PA3PU
0
2
PA2PU
0
1
PA1PU
0
Bit 0
PA0PU
0
Address: $1F00
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SECURE
Write:
SWAIT SPR1
SPR0
LSBF LEVEL
COP
Erased State:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-1. Mask Option Register (MOR)
COP — COP Watchdog Enable
Setting the COP bit will enable the COP watchdog timer. The COP will reset the MCU if the timeout
period is reached before the COP watchdog timer is cleared by the application software and the
voltage applied to the IRQ/V_PP pin is between V_SS and V_DD. Clearing the COP bit will disable the COP
watchdog timer regardless of the voltage applied to the IRQ/V_PP pin.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
63