MC705P6ACPE Datasheet, PDF (22/98 Pages) Freescale Semiconductor, Inc – M68HC05 Microcontrollers

Memory
Addr.
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
Register Name
Port A Data Register
(PORTA)
See page 37.
Port B Data Register
(PORTB)
See page 38.
Port C Data Register
(PORTC)
See page 38.
Port D Data Register
(PORTD)
See page 39.
Port A Data Direction
Register (DDRA)
See page 37.
Port B Data Direction
Register (DDRB)
See page 38.
Port C Data Direction
Register (DDRC)
See page 38.
Port D Data Direction
Register (DDRD)
See page 39.
Unimplemented
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Bit 7
PA7
PB7
PC7
PD7
DDRA7
0
DDRB7
0
DDRC7
0
0
0
6
PA6
PB6
PC6
0
DDRA6
0
DDRB6
0
DDRC6
0
0
0
5
PA5
PB5
PC5
PD5
DDRA5
0
DDRB5
0
DDRC5
0
DDRD5
0
4
3
PA4
PA3
Unaffected by reset
0
0
Unaffected by reset
PC4
PC3
Unaffected by reset
1
0
Unaffected by reset
DDRA4 DDRA3
0
0
1
1
0
DDRC4
0
0
0
DDRC3
0
0
0
0
2
PA2
0
PC2
0
DDRA2
0
1
0
DDRC2
0
0
0
1
PA1
0
PC1
0
DDRA1
0
1
0
DDRC1
0
0
0
Bit 0
PA0
0
PC0
0
DDRA0
0
1
0
DDRC0
0
0
0
$0009
Unimplemented
$000A
$000B
$000C
SIOP Control Register ^Read:
0
SPE
0
0
MSTR
0
(SCR) Write:
See page 43. _Reset:
0
0
0
0
0
0
SIOP Status Register ^{Read: SPIF}
DCOL
0
0
0
0
(SSR) Write:
See page 44. _Reset:
0
0
0
0
0
0
SIOP Data Register
(SDR)
See page 44.
Read:
Write:
Reset:
SDR7
SDR6
SDR5
SDR4 SDR3
Unaffected by reset
SSDR2
= Unimplemented
R
= Reserved
Figure 2-3. I/O and Control Register Summary (Sheet 1 of 3)
0
0
0
0
0
0
0
SDR1
0
SDR0
U = Undetermined
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
22
Freescale Semiconductor