MC705P6ACPE Datasheet, PDF (83/98 Pages) Freescale Semiconductor, Inc – M68HC05 Microcontrollers

Table 13-7. Opcode Map
Bit Manipulation Branch
Read-Modify-Write
Control
Register/Memory
DIR
DIR
REL
DIR
INH
INH
IX1
IX
INH
INH
IMM
DIR
EXT
IX2
IX1
IX
MSB
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
MSB
LSB
LSB
5
5
3
5
3
3
6
5
9
0
BRSET0 BSET0
BRA
NEG
NEGA NEGX
NEG
NEG
RTI
3
DIR 2
DIR 2 REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
INH
2
3
4
5
4
3
SUB
SUB
SUB
SUB
SUB
SUB
0
2 IMM 2
DIR 3 EXT 3
IX2 2
IX1 1
IX
5
5
3
1
BRCLR0 BCLR0
BRN
3
DIR 2
DIR 2 REL
6
RTS
1
INH
2
3
4
5
4
3
CMP
CMP
CMP
CMP
CMP
CMP
1
2 IMM 2
DIR 3 EXT 3
IX2 2
IX1 1
IX
5
5
3
2
BRSET1 BSET1
BHI
3
DIR 2
DIR 2 REL
11
MUL
1
INH
2
3
4
5
4
3
SBC
SBC
SBC
SBC
SBC
SBC
2
2 IMM 2
DIR 3 EXT 3
IX2 2
IX1 1
IX
5
5
3
5
3
3
6
5
10
3
BRCLR1 BCLR1
BLS
COM COMA COMX COM
COM
SWI
3
DIR 2
DIR 2 REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
INH
2
3
4
5
4
3
CPX
CPX
CPX
CPX
CPX
CPX
3
2 IMM 2
DIR 3 EXT 3
IX2 2
IX1 1
IX
5
5
3
5
3
3
6
5
4
BRSET2 BSET2
BCC
LSR
LSRA
LSRX
LSR
LSR
3
DIR 2
DIR 2 REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
2
3
4
5
4
3
AND
AND
AND
AND
AND
AND
4
2 IMM 2
DIR 3 EXT 3
IX2 2
IX1 1
IX
5
5
3
5
BRCLR2 BCLR2 BCS/BLO
3
DIR 2
DIR 2 REL
2
3
4
5
4
3
BIT
BIT
BIT
BIT
BIT
BIT
5
2 IMM 2
DIR 3 EXT 3
IX2 2
IX1 1
IX
5
5
3
5
3
3
6
5
6
BRSET3 BSET3
BNE
ROR
RORA RORX
ROR
ROR
3
DIR 2
DIR 2 REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
2
3
4
5
4
3
LDA
LDA
LDA
LDA
LDA
LDA
6
2 IMM 2
DIR 3 EXT 3
IX2 2
IX1 1
IX
5
5
3
5
3
3
6
5
7
BRCLR3 BCLR3
BEQ
ASR
ASRA ASRX
ASR
ASR
3
DIR 2
DIR 2 REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
2
TAX
1
INH
4
5
6
5
4
STA
STA
STA
STA
STA
7
2
DIR 3 EXT 3
IX2 2
IX1 1
IX
5
5
3
5
3
3
6
5
8
BRSET4 BSET4 BHCC ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL
3
DIR 2
DIR 2 REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
2
2
3
4
5
4
3
CLC
EOR
EOR
EOR
EOR
EOR
EOR
8
1
INH 2 IMM 2
DIR 3 EXT 3
IX2 2
IX1 1
IX
5
5
3
5
3
3
6
5
9
BRCLR4 BCLR4 BHCS
ROL
ROLA ROLX
ROL
ROL
3
DIR 2
DIR 2 REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
2
2
3
4
5
4
3
SEC
ADC
ADC
ADC
ADC
ADC
ADC
9
1
INH 2 IMM 2
DIR 3 EXT 3
IX2 2
IX1 1
IX
5
5
3
5
3
3
6
5
A
BRSET5 BSET5
BPL
DEC
DECA DECX
DEC
DEC
3
DIR 2
DIR 2 REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
B BRCLR5 BCLR5
BMI
3
DIR 2
DIR 2 REL
2
2
3
4
5
4
3
CLI
ORA
ORA
ORA
ORA
ORA
ORA
A
1
INH 2 IMM 2
DIR 3 EXT 3
IX2 2
IX1 1
IX
2
2
3
4
5
4
3
SEI
ADD
ADD
ADD
ADD
ADD
ADD
B
1
INH 2 IMM 2
DIR 3 EXT 3
IX2 2
IX1 1
IX
5
5
3
5
3
3
6
5
C
BRSET6 BSET6
BMC
INC
INCA
INCX
INC
INC
3
DIR 2
DIR 2 REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
2
RSP
1
INH
2
3
4
3
2
JMP
JMP
JMP
JMP
JMP
C
2
DIR 3 EXT 3
IX2 2
IX1 1
IX
5
5
3
4
3
3
5
4
D BRCLR6 BCLR6 BMS
TST
TSTA
TSTX
TST
TST
3
DIR 2
DIR 2 REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
2
6
5
6
7
6
5
NOP
BSR
JSR
JSR
JSR
JSR
JSR
D
1
INH 2 REL 2
DIR 3 EXT 3
IX2 2
IX1 1
IX
5
5
3
E
BRSET7 BSET7
BIL
3
DIR 2
DIR 2 REL
2
STOP
1
INH
2
3
4
5
4
3
LDX
LDX
LDX
LDX
LDX
LDX
E
2 IMM 2
DIR 3 EXT 3
IX2 2
IX1 1
IX
5
5
3
5
3
3
6
5
2
2
F BRCLR7 BCLR7
BIH
CLR
CLRA CLRX
CLR
CLR
WAIT
TXA
3
DIR 2
DIR 2 REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
INH 1
INH
4
5
6
5
4
STX
STX
STX
STX
STX
F
2
DIR 3 EXT 3
IX2 2
IX1 1
IX
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
LSB of Opcode in Hexadecimal
MSB
0
LSB
MSB of Opcode in Hexadecimal
5 Number of Cycles
0
BRSET0 Opcode Mnemonic
3
DIR Number of Bytes/Addressing Mode