MC705P6ACPE Datasheet, PDF (41/98 Pages) Freescale Semiconductor, Inc – M68HC05 Microcontrollers

Chapter 7
Serial Input/Output Port (SIOP)
7.1 Introduction
The simple synchronous serial I/O port (SIOP) subsystem is designed to provide efficient serial
communications between peripheral devices or other MCUs. The SIOP is implemented as a 3-wire
master/slave system with serial clock (SCK), serial data input (SDI), and serial data output (SDO). A block
diagram of the SIOP is shown in Figure 7-1. A mask programmable option determines whether the SIOP
is MSB or LSB first.
The SIOP subsystem shares its input/output pins with port B. When the SIOP is enabled (SPE bit set in
register SCR), port B DDR and data registers are modified by the SIOP. Although port B DDR and data
registers can be altered by application software, these actions could affect the transmitted or received
data.
HCO5 INTERNAL BUS
SPE
76543210
CONTROL
REGISTER
$0A
76543210
76543210
BAUD
STATUS
8-BIT
SDO
I/O
RATE
GENERATOR
REGISTER
SHIFT
REGISTER
SDI
CONTROL
LOGIC
$0B
$0C
INTERNAL
CPU CLOCK
SCK
Figure 7-1. SIOP Block Diagram
SDO/PB5
SDI/PB6
SCK/PB7
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
41