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MC9S12DP256B Datasheet, PDF (76/126 Pages) Freescale Semiconductor, Inc – device made up of standard HCS12 blocks and the HCS12 processor core
MC9S12DP256B Device User GFuirdeee—scV0a2.l1e5 Semiconductor, Inc.
$FFC8, $FFC9
$FFC6, $FFC7
$FFC4, $FFC5
$FFC2, $FFC3
$FFC0, $FFC1
$FFBE, $FFBF
$FFBC, $FFBD
$FFBA, $FFBB
$FFB8, $FFB9
$FFB6, $FFB7
$FFB4, $FFB5
$FFB2, $FFB3
$FFB0, $FFB1
$FFAE, $FFAF
$FFAC, $FFAD
$FFAA, $FFAB
$FFA8, $FFA9
$FFA6, $FFA7
$FFA4, $FFA5
$FFA2, $FFA3
$FFA0, $FFA1
$FF9E, $FF9F
$FF9C, $FF9D
$FF9A, $FF9B
$FF98, $FF99
$FF96, $FF97
$FF94, $FF95
$FF92, $FF93
$FF90, $FF91
$FF8E, $FF8F
$FF8C, $FF8D
$FF80 to
$FF8B
Pulse Accumulator B Overflow
I-Bit
PBCTL(PBOVI)
$C8
CRG PLL lock
I-Bit
CRGINT(LOCKIE)
$C6
CRG Self Clock Mode
I-Bit
CRGINT (SCMIE)
$C4
BDLC
I-Bit
DLCBCR1(IE)
$C2
IIC Bus
I-Bit
IBCR (IBIE)
$C0
SPI1
I-Bit
SP1CR1 (SPIE, SPTIE)
$BE
SPI2
I-Bit
SP2CR1 (SPIE, SPTIE)
$BC
EEPROM
I-Bit
EECTL(CCIE, CBEIE)
$BA
FLASH
I-Bit
FCTL(CCIE, CBEIE)
$B8
CAN0 wake-up
I-Bit
CAN0RIER (WUPIE)
$B6
CAN0 errors
I-Bit CAN0RIER (CSCIE, OVRIE)
$B4
CAN0 receive
I-Bit
CAN0RIER (RXFIE)
$B2
CAN0 transmit
I-Bit CAN0TIER (TXEIE2-TXEIE0)
$B0
CAN1 wake-up
I-Bit
CAN1RIER (WUPIE)
$AE
CAN1 errors
I-Bit CAN1RIER (CSCIE, OVRIE)
$AC
CAN1 receive
I-Bit
CAN1RIER (RXFIE)
$AA
CAN1 transmit
I-Bit CAN1TIER (TXEIE2-TXEIE0)
$A8
CAN2 wake-up
I-Bit
CAN2RIER (WUPIE)
$A6
CAN2 errors
I-Bit CAN2RIER (CSCIE, OVRIE)
$A4
CAN2 receive
I-Bit
CAN2RIER (RXFIE)
$A2
CAN2 transmit
I-Bit CAN2TIER (TXEIE2-TXEIE0)
$A0
CAN3 wake-up
I-Bit
CAN3RIER (WUPIE)
$9E
CAN3 errors
I-Bit CAN3RIER (TXEIE2-TXEIE0)
$9C
CAN3 receive
I-Bit
CAN3RIER (RXFIE)
$9A
CAN3 transmit
I-Bit CAN3TIER (TXEIE2-TXEIE0)
$98
CAN4 wake-up
I-Bit
CAN4RIER (WUPIE)
$96
CAN4 errors
I-Bit CAN4RIER (CSCIE, OVRIE)
$94
CAN4 receive
I-Bit
CAN4RIER (RXFIE)
$92
CAN4 transmit
I-Bit CAN4TIER (TXEIE2-TXEIE0)
$90
Port P Interrupt
I-Bit
PTPIF (PTPIE)
$8E
PWM Emergency Shutdown
I-Bit
PWMSDN (PWMIE)
$8C
Reserved
5.3 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module Block User Guides for register reset states.
5.3.1 I/O pins
Refer to the HCS12 Core User Guides for mode dependent pin configuration of port A, B, E and K out of
reset.
Refer to the PIM Block User Guide for reset configurations of all peripheral module ports.
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