MC9S12DP256B Datasheet, PDF (107/126 Pages) Freescale Semiconductor, Inc – device made up of standard HCS12 blocks and the HCS12 processor core

Freescale Semicon_Md_Cu₉c_S1t₂o_Dr_P,₂I₅n_6Bc_D._{evice User Guide — V02.15}
A.5.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO)
is also the system clock source in self clock mode.
A.5.3.1 XFC Component Selection
This section describes the selection of the XFC components to achieve a good filter characteristics.
VDDPLL
C_s
C_p
R
f_osc
1
f_ref
refdv+1
Phase
∆
K_Φ
VCO
K_V
f_vco
Detector
f_cmp
Loop Divider
1
1
synr+1
2
Figure A-2 Basic PLL functional diagram
The following procedure can be used to calculate the resistance and capacitance values using typical
values for K₁, f₁ and i_ch from Table A-16.
The VCO Gain at the desired VCO output frequency is approximated by:
K_V = K₁ ⋅ e^{-(--fK--1--1--–--⋅--f-1-v--c-V--o--)-}
The phase detector relationship is given by:
i_ch is the current in tracking mode.
K_Φ = – i_ch ⋅ K_V
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