MC9S12DP256B Datasheet, PDF (2/126 Pages) Freescale Semiconductor, Inc – device made up of standard HCS12 blocks and the HCS12 processor core

Freescale Semiconductor, Inc.
DOCUMENT NUMBER
9S12DP256BDGV2/D
Revision History
Version Revision Effective
Number Date
Date
V01.00
29 MAR 29 MAR
2001
2001
V01.01
8 MAY
2001
8 MAY
2001
V02.00
16 May
2001
16 May
2001
V02.01
V02.02
V02.03
5 June
2001
14 June
2001
18 June
2001
V02.04
26 June
2001
V02.05
V02.06
11 July
2001
17 July
2001
V02.07
24 July
2001
Author
Description of Changes
Initial version.
VDD5 spec change 4.5V . . 5.25V
Current Injection on single pin +- 2.5mA
added DC bias level on EXTAL pin
minor cosmetics and corrected typos
changed ATD Electrical Characteristics seperate coupling ratio for
positive and negative bulk current injection
added pinout for 80QFP
corrected SPI timing
corrected Expanded Bus Timing Characteristics
Some corrections on pin usage after review
Minor corrections with respect to format and wording
Added SRAM data retention disclaimer
Changed Oscillator Characteristics t_CQOUT max 2.5s and replaced
Clock Monitor Time-out by Clock Monitor Failure Assert Frequency
Changed Self Clock Mode Frequency min 1MHz and max 5.5MHz
Changed I_DDPS (RTI and COP disabled) to 400uA
Corrected f_ref and REFDV/SYNR Settings for PLL Stabilization
Delay Measurements, added t_EXTR and t_EXTF to Oscillator
Characteristics, Corrected t_EXTL and t_EXTH values
Added thermal resistance for LQFP 80, added PCB layout proposal
for power and ground connections
Added Document Names
Variable definitions and Names have been hidden
Added Maskset 1K79X
Modified description in chapter A.5.2 Oscillator
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2
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