MC9S12DP256B Datasheet, PDF (117/126 Pages) Freescale Semiconductor, Inc – device made up of standard HCS12 blocks and the HCS12 processor core

Freescale Semicon_Md_Cu₉c_S1t₂o_Dr_P,₂I₅n_6Bc_D._{evice User Guide — V02.15}
A.8 External Bus Timing
A timing diagram of the external multiplexed-bus is illustrated in Figure A-9 with the actual timing
values shown on table Table A-20. All major bus signals are included in the diagram. While both a data
write and data read cycle are shown, only one or the other would occur on a particular bus cycle.
A.8.1 General Muxed Bus Timing
The expanded bus timings are highly dependent on the load conditions. The timing parameters shown
assume a balanced load across all outputs.
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