MC9S12DP256B Datasheet, PDF (115/126 Pages) Freescale Semiconductor, Inc – device made up of standard HCS12 blocks and the HCS12 processor core

Freescale Semicon_Md_Cu₉c_S1t₂o_Dr_P,₂I₅n_6Bc_D._{evice User Guide — V02.15}
A.7.2 Slave Mode
Figure A-7 and Figure A-8 illustrate the slave mode timing. Timing values are shown in Table A-19.
SS
(INPUT)
SCK
(CPOL = 0)
(INPUT)
SCK
(CPOL = 1)
(INPUT)
1
12
2
4
4
11
11 3
12
8
7
9
10
10
MISO
(OUTPUT)
SLAVE MSB OUT
BIT 6 . . . 1
SLAVE LSB OUT
MOSI
(INPUT)
5
6
MSB IN
BIT 6 . . . 1
LSB IN
Figure A-7 SPI Slave Timing (CPHA = 0)
SS
(INPUT)
SCK
(CPOL = 0)
(INPUT)
SCK
(CPOL = 1)
(INPUT)
MISO
(OUTPUT)
MOSI
(INPUT)
1
2
12
4
4
11
9
SLAVE MSB OUT
7
5
6
MSB IN
10
BIT 6 . . . 1
BIT 6 . . . 1
3
11
12
8
SLAVE LSB OUT
LSB IN
Figure A-8 SPI Slave Timing (CPHA =1)
117
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