MC9S12DP256B Datasheet, PDF (69/126 Pages) Freescale Semiconductor, Inc – device made up of standard HCS12 blocks and the HCS12 processor core

Freescale Semicon_Md_Cu₉c_S1t₂o_Dr_P,₂I₅n_6Bc_D._{evice User Guide — V02.15}
Section 3 System Clock Description
3.1 Overview
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules.
Figure 3-1 shows the clock connections from the CRG to all modules.
Consult the CRG Block User Guide for details on clock generation.
1/2
BDM
core clock
S12_CORE
EXTAL
XTAL
CRG
bus clock
oscillator clock
Flash
RAM
EEPROM
ECT
ATD0, 1
PWM
SCI0, SCI1
SPI0, 1, 2
CAN0, 1, 2, 3, 4
IIC
BDLC
PIM
Figure 3-1 Clock Connections
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