MC9S12DP256B Datasheet, PDF (101/126 Pages) Freescale Semiconductor, Inc – device made up of standard HCS12 blocks and the HCS12 processor core

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3. Maximum Erase and Programming times are achieved under particular combinations of f_NVMOP and bus frequency f_bus.
Refer to formulae in Sections A.3.1.1 - A.3.1.4 for guidance.
4. urst Programming operations are not applicable to EEPROM
5. Minimum Erase times are achieved under maximum NVM operating frequency f_NVMOP.
6. Minimum time, if first word in the array is not blank
7. Maximum time to complete check on an erased block
A.3.2 NVM Reliability
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process
monitors and burn-in to screen early life failures.
The failure rates for data retention and program/erase cycling are specified at the operating conditions
noted.
The program/erase cycle count on the sector is incremented every time a sector or mass erase event is
executed.
NOTE: All values shown in Table A-12 are target values and subject to further extensive
characterization.
Table A-12 NVM Reliability Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
1 C Flash/EEPROM (-40C to + 125C)
2 C EEPROM (-40C to + 125C)
Cycles
10
10,000
Data
Retention
Lifetime
15
5
Unit
Years
Years
NOTE: Flash cycling performance is 10 cycles at -40C to + 125C. Data retention is
specified for 15 years.
NOTE: EEPROM cycling performance is 10K cycles at -40C to +125C. Data retention is
specified for 5 years on words after cycling 10K times. However if only 10 cycles
are executed on a word the data retention is specified for 15 years.
103
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