MC9S12DP256B Datasheet, PDF (57/126 Pages) Freescale Semiconductor, Inc – device made up of standard HCS12 blocks and the HCS12 processor core

Freescale Semicon_Md_Cu₉c_S1t₂o_Dr_P,₂I₅n_6Bc_D._{evice User Guide — V02.15}
Pin Name Pin Name Pin Name Pin Name Pin Name Power
Funct. 1 Funct. 2 Funct. 3 Funct. 4 Funct. 5 Supply
Internal Pull
Resistor
CTRL
Reset
State
Description
PP6
KWP6
PWM6
SS2
PERP/
Port P I/O, Interrupt, Channel 6 of
—
VDDX
PPSP
Disabled
PWM, SS of SPI2
PERP/
Port P I/O, Interrupt, Channel 5 of
PP5
KWP5
PWM5
MOSI2
—
VDDX
PPSP
Disabled
PWM, MOSI of SPI2
PERP/
Port P I/O, Interrupt, Channel 4 of
PP4
KWP4
PWM4
MISO2
—
VDDX
PPSP
Disabled
PWM, MISO2 of SPI2
PP3
KWP3
PWM3
SS1
PERP/
Port P I/O, Interrupt, Channel 3 of
—
VDDX
PPSP
Disabled
PWM, SS of SPI1
PP2
KWP2
PWM2
SCK1
PERP/
Port P I/O, Interrupt, Channel 2 of
—
VDDX
PPSP
Disabled
PWM, SCK of SPI1
PERP/
Port P I/O, Interrupt, Channel 1 of
PP1
KWP1
PWM1
MOSI1
—
VDDX
PPSP
Disabled
PWM, MOSI of SPI1
PERP/
Port P I/O, Interrupt, Channel 0 of
PP0
KWP0
PWM0
MISO1
—
VDDX
PPSP
Disabled
PWM, MISO2 of SPI1
PERS/
PS7
SS0
—
—
—
VDDX _PPSS
Up Port S I/O, SS of SPI0
PERS/
PS6
SCK0
—
—
—
VDDX
PPSS
Up Port S I/O, SCK of SPI0
PERS/
PS5
MOSI0
—
—
—
VDDX _PPSS
Up Port S I/O, MOSI of SPI0
PERS/
PS4
MISO0
—
—
—
VDDX _PPSS
Up Port S I/O, MISO of SPI0
PERS/
PS3
TXD1
—
—
—
VDDX _PPSS
Up Port S I/O, TXD of SCI1
PERS/
PS2
RXD1
—
—
—
VDDX
PPSS
Up Port S I/O, RXD of SCI1
PERS/
PS1
TXD0
—
—
—
VDDX _PPSS
Up Port S I/O, TXD of SCI0
PERS/
PS0
RXD0
—
—
—
VDDX _PPSS
Up Port S I/O, RXD of SCI0
PERT/
PT[7:0]
IOC[7:0]
—
—
—
VDDX _PPST Disabled Port T I/O, Timer channels
2.3 Detailed Signal Descriptions
2.3.1 EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output.
59
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