K40P81M100SF2_11 Datasheet, PDF (58/63 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

Pinout
81 80 Pin Name Default
ALT0
ALT1
MAP LQF
BGA P
• 42 RESET_b RESET_b RESET_b
• 43 PTB0
LCD_P0/ LCD_P0/ PTB0
ADC0_SE8/ ADC0_SE8/
ADC1_SE8/ ADC1_SE8/
TSI0_CH0 TSI0_CH0
• 44 PTB1
LCD_P1/ LCD_P1/ PTB1
ADC0_SE9/ ADC0_SE9/
ADC1_SE9/ ADC1_SE9/
TSI0_CH6 TSI0_CH6
• 45 PTB2
LCD_P2/ LCD_P2/ PTB2
ADC0_SE1 ADC0_SE1
2/TSI0_CH7 2/TSI0_CH7
• 46 PTB3
LCD_P3/ LCD_P3/ PTB3
ADC0_SE1 ADC0_SE1
3/TSI0_CH8 3/TSI0_CH8
• 47 PTB8
LCD_P8 LCD_P8 PTB8
• 48 PTB9
LCD_P9 LCD_P9 PTB9
• 49 PTB10
• 50 PTB11
• 51 PTB16
• 52 PTB17
• 53 PTB18
• 54 PTB19
• 55 PTC0
• 56 PTC1
• 57 PTC2
• 58 PTC3
• 59 VSS
LCD_P10/ LCD_P10/ PTB10
ADC1_SE1 ADC1_SE1
4
4
LCD_P11/ LCD_P11/ PTB11
ADC1_SE1 ADC1_SE1
5
5
LCD_P12/ LCD_P12/ PTB16
TSI0_CH9 TSI0_CH9
LCD_P13/ LCD_P13/ PTB17
TSI0_CH10 TSI0_CH10
LCD_P14/ LCD_P14/ PTB18
TSI0_CH11 TSI0_CH11
LCD_P15/ LCD_P15/ PTB19
TSI0_CH12 TSI0_CH12
LCD_P20/ LCD_P20/ PTC0
ADC0_SE1 ADC0_SE1
4/
4/
TSI0_CH13 TSI0_CH13
LCD_P21/ LCD_P21/ PTC1
ADC0_SE1 ADC0_SE1
5/
5/
TSI0_CH14 TSI0_CH14
LCD_P22/ LCD_P22/ PTC2
ADC0_SE4 ADC0_SE4
b/
b/
CMP1_IN0/ CMP1_IN0/
TSI0_CH15 TSI0_CH15
LCD_P23/ LCD_P23/ PTC3
CMP1_IN1 CMP1_IN1
VSS
VSS
ALT2
ALT3
ALT4
I2C0_SCL FTM1_CH0
I2C0_SDA FTM1_CH1
I2C0_SCL UART0_RT
S_b
I2C0_SDA UART0_CT
S_b
UART3_RT
S_b
SPI1_PCS1 UART3_CT
S_b
SPI1_PCS0 UART3_RX
SPI1_SCK UART3_TX
SPI1_SOUT UART0_RX
SPI1_SIN UART0_TX
CAN0_TX
CAN0_RX
SPI0_PCS4
FTM2_CH0
FTM2_CH1
PDB0_EXT
RG
I2S0_TX_B
CLK
I2S0_TX_F
S
I2S0_TXD
SPI0_PCS3 UART1_RT FTM0_CH0
S_b
SPI0_PCS2 UART1_CT FTM0_CH1
S_b
SPI0_PCS1 UART1_RX FTM0_CH2
ALT5
ALT6
ALT7
FTM1_QD_ LCD_P0
PHA
FTM1_QD_ LCD_P1
PHB
FTM0_FLT3 LCD_P2
FTM0_FLT0 LCD_P3
LCD_P8
LCD_P9
FTM0_FLT1 LCD_P10
FTM0_FLT2 LCD_P11
EWM_IN LCD_P12
EWM_OUT
_b
FTM2_QD_
PHA
FTM2_QD_
PHB
LCD_P13
LCD_P14
LCD_P15
LCD_P20
LCD_P21
LCD_P22
LCD_P23
EzPort
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
58
Preliminary
Freescale Semiconductor, Inc.