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K40P81M100SF2_11 Datasheet, PDF (13/63 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz | |||
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⢠CPU and system clocks = 100 MHz
⢠Bus clock = 50 MHz
⢠Flash clock = 25 MHz
Symbol
tPOR
Table 5. Power mode transition operating behaviors
Description
Min.
Max.
Unit
After a POR event, amount of time from the point VDD
â
300
μs
reaches 1.8V to execution of the first instruction
across the operating temperature range of the chip.
RUN â VLLS1 â RUN
⢠RUN â VLLS1
â
4.1
μs
⢠VLLS1 â RUN
â
123.8
μs
RUN â VLLS2 â RUN
⢠RUN â VLLS2
⢠VLLS2 â RUN
â
4.1
μs
â
49.3
μs
RUN â VLLS3 â RUN
⢠RUN â VLLS3
⢠VLLS3 â RUN
â
4.1
μs
â
49.2
μs
RUN â LLS â RUN
⢠RUN â LLS
⢠LLS â RUN
â
4.1
μs
â
5.9
μs
RUN â STOP â RUN
⢠RUN â STOP
⢠STOP â RUN
â
4.1
μs
â
4.2
μs
RUN â VLPS â RUN
⢠RUN â VLPS
⢠VLPS â RUN
â
4.1
μs
â
5.8
μs
1. Normal boot (FTFL_OPT[LPBOOT]=1)
General
Notes
1
5.1.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol Description
IDDA Analog supply current
Min.
Typ.
Max.
Unit
â
â
TBD
mA
Table continues on the next page...
Notes
1
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
13
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