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6.8.9 SDHC specifications
Peripheral operating requirements and behaviors
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 40. SDHC switching specifications
Num
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
Symbol Description
Min.
Max.
Operating voltage
2.7
3.6
Card input clock
fpp
Clock frequency (low speed)
0
400
fpp
Clock frequency (SD\SDIO full speed)
0
25
fpp
Clock frequency (MMC full speed)
0
20
f_OD
Clock frequency (identification mode)
0
400
t_WL
Clock low time
7
—
t_WH
Clock high time
7
—
t_TLH
Clock rise time
—
3
t_THL
Clock fall time
—
3
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
t_OD
SDHC output delay (output valid)
-5
6.5
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
t_THL
SDHC input setup time
5
—
t_THL
SDHC input hold time
0
—
Unit
V
kHz
MHz
MHz
kHz
ns
ns
ns
ns
ns
ns
ns
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
Input SDHC_DAT[3:0]
SD3
SD2
SD6
SD7
SD1
SD8
Figure 23. SDHC timing
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
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