K40P81M100SF2_11 Datasheet, PDF (36/63 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

Peripheral operating requirements and behaviors
FIGURE TBD
Figure 12. Typical ENOB vs. Averaging for 16-bit differential and 16-bit single-ended
modes
6.6.1.3 16-bit ADC with PGA operating conditions
Table 25. 16-bit ADC with PGA operating conditions
Symbol
V_DDA
V_REFPGA
V_ADIN
V_CM
R_PGAD
R_AS
T_S
Description
Supply voltage
PGA ref voltage
Input voltage
Input Common
Mode range
Differntial input
impedance
Analog source
resistance
ADC sampling
time
Conditions
Absolute
Gain = 1, 2, 4, 8
Gain = 16, 32
Gain = 64
Min.
Typ.¹
Max.
1.71
—
3.6
VREFOUT VREFOUT VREFOUT
V_SSA
—
V_DDA
V_SSA
—
V_DDA
—
128
—
—
64
—
—
32
—
—
100
—
Unit
V
V
V
V
kΩ
Ω
1.25
—
—
µs
Notes
2, 3
IN+ to IN-⁴
5
6
1. Typical values assume V_DDA = 3.0 V, Temp = 25°C, f_ADCK = 6 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. ADC must be configured to use the internal voltage reference (VREFOUT)
3. PGA reference connected to the VREFOUT pin. If the user wishes to drive VREFOUT with a voltage other than the output
of the VREF module, the VREF module must be disabled.
4. For single ended configurations the input impedence of the driven input is 1/2.
5. The analog source resistance (R_AS), external to MCU, should be kept as minimum as possible. Increased R_AS causes drop
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
time should be allowed for F_in=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
8 MHz ADC clock.
6.6.1.4 16-bit ADC with PGA characteristics
Table 26. 16-bit ADC with PGA characteristics
Symbol
I_{DDA_PGA}
I_{DC_PGA}
Description
Supply current
Input DC current
Conditions
Min.
Typ.¹
Max.
Unit
—
590
TBD
μA
A
I_ILKG
Input Leakage
current
PGA disabled
—
TBD
TBD
μA
Table continues on the next page...
Notes
2
3
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
36
Preliminary
Freescale Semiconductor, Inc.