K40P81M100SF2_11 Datasheet, PDF (21/63 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

Symbol
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
Peripheral operating requirements and behaviors
Table 11. JTAG limited voltage range electricals (continued)
Description
TCLK clock pulse width
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
Min.
Max.
Unit
ns
50
—
20
—
10
TCLK rise and fall times
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
—
3
ns
20
—
ns
0
—
ns
—
25
ns
—
25
ns
8
—
ns
1
—
ns
—
17
ns
—
17
ns
100
—
ns
8
—
ns
Symbol
J1
J2
J3
J4
J5
J6
J7
J8
J9
Table 12. JTAG full voltage range electricals
Description
Operating voltage
Min.
1.71
TCLK frequency of operation
• Boundary Scan
0
• JTAG and CJTAG
0
• Serial Wire Debug
0
TCLK cycle period
1/J1
TCLK clock pulse width
• Boundary Scan
50
• JTAG and CJTAG
25
• Serial Wire Debug
12.5
TCLK rise and fall times
—
Boundary scan input data setup time to TCLK rise
20
Boundary scan input data hold time after TCLK rise
0
TCLK low to boundary scan output data valid
—
TCLK low to boundary scan output high-Z
—
TMS, TDI input data setup time to TCLK rise
8
Table continues on the next page...
Max.
3.6
10
20
40
—
—
—
3
—
—
25
25
—
Unit
V
MHz
ns
ns
ns
ns
ns
ns
ns
ns
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
21